LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 504

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 428. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description
<Document ID>
User manual
Bit
13
16:14
19:17
20
21
23:22
Symbol
ST
TTC
-
FTF
TSF
-
Description
Start/Stop Transmission Command
When this bit is set, transmission is placed in the Running state, and the DMA checks
the Transmit List at the current position for a frame to be transmitted. Descriptor
acquisition is attempted either from the current position in the list, which is the
Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from
the position retained when transmission was stopped previously. If the current
descriptor is not owned by the DMA, transmission enters the Suspended state and
Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission
command is effective only when transmission is stopped. If the command is issued
before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is
unpredictable.
When this bit is reset, the transmission process is placed in the Stopped state after
completing the transmission of the current frame. The Next Descriptor position in the
Transmit List is saved, and becomes the current position when transmission is
restarted. The stop transmission command is effective only the transmission of the
current frame is complete or when the transmission is in the Suspended state.
Transmit threshold control
These three bits control the threshold level of the MTL Transmit FIFO. Transmission
starts when the frame size within the MTL Transmit FIFO is larger than the threshold.
In addition, full frames with a length less than the threshold are also transmitted.
These bits are used only when the TSF bit (Bit 21) is reset.
000 = 64
001 = 128
010 = 192
011 = 256
100 = 40
101 = 32
110 = 24
111 = 16
Reserved
Flush transmit FIFO
When this bit is set, the transmit FIFO controller logic is reset to its default values and
thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the
flushing operation is completed fully. The Operation Mode register should not be
written to until this bit is cleared. The data which is already accepted by the MAC
transmitter will not be flushed. It will be scheduled for transmission and will result in
underflow and runt frame transmission.
Remark: The flush operation completes only after emptying the TxFIFO of its
contents and all the pending Transmit Status of the transmitted frames are accepted
by the host. In order to complete this flush operation, the PHY transmit clock is
required to be active.
Transmit store and forward
When this bit is set, transmission starts when a full frame resides in the MTL Transmit
FIFO. When this bit is set, the TTC values specified in this register (bits [16:14]) are
ignored. This bit should be changed only when transmission is stopped.
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
…continued
Reset
value
0
0
0
0
0
0
504 of 1164
Access
R/W
R/W
RO
R/WS/
SC
R/W
RO