LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 607

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.6.20 SCT capture registers 0 to 15 (REGMODEn bit = 1)
24.6.21 SCT match reload registers 0 to 15 (REGMODEn bit = 0)
There is no “write-through” from Reload registers to Match registers. Before starting a
counter, software can write one value to the Match register that will be used in the first
cycle of the counter, and a different value to the corresponding Match Reload register that
will be used in the second cycle.
Table 519. SCT match registers 0 to 15 (MATCH - address 0x4000 0100 (MATCH0) to 0x4000
These register(s) allow software to read the counter value(s) at which the event selected
by the corresponding Capture Control register(s) occurred.
Table 520. SCT capture registers 0 to 15 (CAP - address 0x4000 0100 (CAP0) to 0x4000 013C
A Match register (L, H, or unified 32-bit) is loaded from the corresponding Reload register
when BIDIR is 0 and the counter reaches its limit condition, or when BIDIR is 1 and the
counter reaches 0.
Table 521. SCT match reload registers 0 to 15 (MATCHREL- address 0x4000 0200
Bit
15:0
31:16
Bit
15:0
31:16
Bit
15:0
31:16 RELOADn_H When UNIFY = 0, read or write the 16-bit to be loaded into the
Symbol
RELOADn_L When UNIFY = 0, read or write the 16-bit value to be loaded into
Symbol
MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to
MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to
Symbol
CAPn_L
CAPn_H
4013C (MATCH15)) bit description (REGMODEn bit = 0)
(CAP15)) bit description (REGMODEn bit = 1)
(MATCHRELOAD0) to 0x4000 023C (MATCHRELOAD15) bit description
(REGMODEn bit = 0)
All information provided in this document is subject to legal disclaimers.
Description
the L counter. When UNIFY = 1, read or write the lower 16 bits of
the 32-bit value to be compared to the unified counter.
the H counter. When UNIFY = 1, read or write the upper 16 bits of
the 32-bit value to be compared to the unified counter.
Description
When UNIFY = 0, read the 16-bit counter value at which this
register was last captured. When UNIFY = 1, read the lower 16 bits
of the 32-bit value at which this register was last captured.
When UNIFY = 0, read the 16-bit counter value at which this
register was last captured. When UNIFY = 1, read the upper 16 bits
of the 32-bit value at which this register was last captured.
Description
the SCTMATCHn_L register. When UNIFY = 1, read or write the
lower 16 bits of the 32-bit value to be loaded into the MATCHn
register.
MATCHn_H register. When UNIFY = 1, read or write the upper 16
bits of the 32-bit value to be loaded into the MATCHn register.
Rev. 00.13 — 20 July 2011
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
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