LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 186

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
13.3.3 I
13.3.4 USB1 DP1/DM1 pins
13.3.5 EMC signal delay control
The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no
pull-up/pull-down. The default value is pull-up enabled.
The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables
the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last
known state if it is configured as an input and is not driven externally. Repeater mode may
typically be used to prevent a pin from floating (and potentially using significant power if it
floats to an indeterminate state) if it is temporarily not driven.
The EHS bits of the SFSI2C0 register
The input signal to the USB1 is controlled by the SFSUSB register
USB_ESEA bit in this register must be set to one to enable the USB1 block.
The SCU contains a programmable delay control for all EMC input and output data,
address, and control signals. For detail on use of the EMC delay modes, see
2
•
•
C0-bus pins
Standard mode/Fast-mode I
I
Fast-mode Plus and High-speed mode (this includes an open-drain output according
to the I
2
C-bus specification).
2
C-bus specification).
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
2
C (this includes an open-drain output according to the
Chapter 13: LPC18xx System Control Unit (SCU)
(Table
120) configure different I
(Table
2
UM10430
C-modes:
© NXP B.V. 2011. All rights reserved.
119). The
Table
186 of 1164
271.