LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 868

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
37.9 I
<Document ID>
User manual
2
C implementation and operation
37.8.4 Slave Transmitter mode
The first byte is received and handled as in the slave receiver mode. However, in this
mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via
SDA while the serial clock is input through SCL. START and STOP conditions are
recognized as the beginning and end of a serial transfer. In a given application, I
operate as a master and as a slave. In the slave mode, the I
slave address and the General Call address. If one of these addresses is detected, an
interrupt is requested. When the microcontrollers wishes to become the bus master, the
hardware waits until the bus is free before the master mode is entered so that a possible
slave action is not interrupted. If bus arbitration is lost in the master mode, the I
interface switches to the slave mode immediately and can detect its own slave address in
the same serial transfer.
Figure 137
text describes the individual blocks.
Fig 136. Format of Slave Transmitter mode
S
from Master to Slave
from Slave to Master
SLAVE ADDRESS
shows how the on-chip I
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
RW=1
2
C-bus interface is implemented, and the following
A
DATA
Chapter 37: LPC18xx I2C-bus interface
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
n bytes data transmitted
A
2
C hardware looks for its own
DATA
UM10430
© NXP B.V. 2011. All rights reserved.
A
2
868 of 1164
C
2
C may
P