LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1085

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 1016.CAN control registers (CNTL, address 0x400E 2000) bit description
Remark: The busoff recovery sequence (see CAN Specification Rev. 2.0 ) cannot be
shortened by setting or resetting the INIT bit. If the device goes into busoff state, it will set
INIT, stopping all bus activities. Once INIT has been cleared by the CPU, the device will
then wait for 129 occurrences of Bus Idle (129  11 consecutive HIGH/recessive bits)
before resuming normal operations. At the end of the busoff recovery sequence, the Error
Management Counters will be reset.
Bit
0
1
2
3
4
5
6
7
31:8
Symbol Value
INIT
IE
SIE
EIE
-
DAR
CCE
TEST
-
All information provided in this document is subject to legal disclaimers.
1
0
1
0
1
0
1
0
-
1
0
1
0
1
0
Rev. 00.13 — 20 July 2011
Test mode enable
Description
Initialization
Initialization is started. On reset, software
needs to initialize the CAN controller.
Normal operation.
Module interrupt enable
Enable CAN interrupts. The interrupt line is set
to LOW and remains LOW until all pending
interrupts are cleared.
Disable CAN interrupts. The interrupt line is
always HIGH.
Status change interrupt enable
Enable status change interrupts. A status
change interrupt will be generated when a
message transfer is successfully completed or
a CAN bus error is detected.
Disable status change interrupts. No status
change interrupt will be generated.
Error interrupt enable
Enable error interrupt. A change in the bits
BOFF or EWARN in the CANSTAT registers
will generate an interrupt.
Disable error interrupt. No error status interrupt
will be generated.
reserved
Disable automatic retransmission
Automatic retransmission disabled.
Automatic retransmission of disturbed
messages enabled.
Configuration change enable
The CPU has write access to the CANBT
register while the INIT bit is one.
The CPU has no write access to the bit timing
register.
Test mode.
Normal operation.
reserved
Chapter 42: Appendix
Reset
value
1
0
0
0
0
0
0
-
0
UM10430
© NXP B.V. 2011. All rights reserved.
1085 of 1164
Access
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
-