LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1069

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 999. I2S DMA Configuration register 1 (DMA1 - address 0x400A 2014) bit description
Table 1000.I2S DMA Configuration register 2 (DMA2 - address 0x400A 2018) bit description
Table 1001.I2S Interrupt Request Control register (IRQ - address 0x400A 201C) bit description
<Document ID>
User manual
Bit
0
1
7:2
11:8
15:12
19:16
31:20
Bit
0
1
7:2
11:8
15:12
19:16
31:20
Bit
0
1
7:2
11:8
Symbol
RX_DMA1_ENABLE
TX_DMA1_ENABLE
-
RX_DEPTH_DMA1
-
TX_DEPTH_DMA1
-
Symbol
RX_DMA2_ENABLE
TX_DMA2_ENABLE
-
RX_DEPTH_DMA2
-
TX_DEPTH_DMA2
-
Symbol
RX_IRQ_ENABLE
TX_IRQ_ENABLE
-
RX_DEPTH_IRQ
42.9.6.7 I2S DMA Configuration Register 2
42.9.6.8 I2S Interrupt Request Control register
The DMA2 register controls the operation of DMA request 2. The function of bits in DMA2
are shown in
This register enables the DMA for the I
FIFO level.
Remark: The FIFOs contain eight 16-bit words. Therefore, if the I
configured for 32-bit mode (see
level is 4.
The IRQ register controls the operation of the I2S interrupt request. The function of bits in
IRQ are shown in
Description
When 1, enables I2S receive interrupt.
When 1, enables I2S transmit interrupt.
Reserved.
Set the FIFO level on which to create an irq request.
Description
When 1, enables DMA1 for I2S receive.
When 1, enables DMA1 for I2S transmit.
Reserved.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Set the FIFO level that triggers a receive DMA request on DMA2.
Set the FIFO level that triggers a transmit DMA request on DMA2.
Description
When 1, enables DMA1 for I2S receive.
When 1, enables DMA1 for I2S transmit.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Set the FIFO level that triggers a receive DMA request on DMA1.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Set the FIFO level that triggers a transmit DMA request on DMA1.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Table
All information provided in this document is subject to legal disclaimers.
Table
994.
Rev. 00.13 — 20 July 2011
994.
Table 994
2
S receive and transmit channels and sets the
and
Table
995), the maximum allowed FIFO
2
Chapter 42: Appendix
S controller is
UM10430
© NXP B.V. 2011. All rights reserved.
1069 of 1164
Reset
value
0
0
-
-
0
0
0
Reset
value
0
0
0
0
-
0
-
Reset
value
0
0
0
0