LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 541

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
23.4 General description
<Document ID>
User manual
23.4.1 Programmable parameters
23.4.2 Hardware cursor support
The following key display and controller parameters can be programmed:
The hardware cursor feature reduces software overhead associated with maintaining a
cursor image in the LCD frame buffer.
Without this feature, software needed to:
In addition, the LCD driver had to check whether the graphics operation had overwritten
the cursor, and correct it. With a cursor size of 64x64 and 24-bit color, each cursor move
involved reading and writing approximately 75 kB of data.
The hardware cursor removes the requirement for this management by providing a
completely separate image buffer for the cursor, and superimposing the cursor image on
the LCD output stream at the current cursor (X,Y) coordinate.
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LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.
Horizontal front and back porch
Horizontal synchronization pulse width
Number of pixels per line
Vertical front and back porch
Vertical synchronization pulse width
Number of lines per panel
Number of pixel clocks per line
Hardware cursor control.
Signal polarity, active HIGH or LOW
AC panel bias
Panel clock frequency
Bits-per-pixel
Display type: STN monochrome, STN color, or TFT
STN 4 or 8-bit interface mode
STN dual or single panel mode
Little-endian, big-endian, or Windows CE mode
Interrupt generation event
Save an image of the area under the next cursor position.
Update the area with the cursor image.
Repair the last cursor position with a previously saved image.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
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