LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 988

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.4.6.4.1 PLL1 status register
42.4.6.4.2 PLL1 control register
42.4.6.4 PLL1 registers
The PLL1 is used for the core and all peripheral blocks.
Table 937. PLL1_STAT register (PLL1_STAT, address 0x4005 002C) bit description
Table 938. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0030) bit description
Bit
0
31:1
Bit
0
1
2
5:3
6
7
9:8
10
11
Symbol
PD
BYPASS
-
-
FBSEL
DIRECT
PSEL[1:0]
-
AUTOBLOCK
Symbol
LOCK
-
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value Description
0
1
0
1
0
1
0
1
0x0
0x1
0x2
0x3
0
1
Description
PLL1 lock indicator
Reserved
PLL1 power down
PLL1 enabled
PLL1 powered down
Input clock bypass control
CCO clock sent to post-dividers. Use for
normal operation.
PLL1 input clock sent to post-dividers
(default).
Reserved. Do not write one to this bit.
Reserved. Do not write one to these bits.
PLL feedback select (see
block
CCO output is used as feedback divider input
clock.
PLL output clock (clkout) is used as feedback
divider input clock. Use for normal operation.
PLL direct CCO output
Disabled
Enabled
Post-divider division ratio. The value applied
is 2xP.
1
2 (default)
4
8
Reserved
Block clock automatically during frequency
change
Autoblocking disabled
Autoblocking enabled
diagram”).
Figure 155 “PLL1
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
1
-
Reset
value
1
1
0
-
0
0
01
-
0
988 of 1164
Access
R
-
Access
R/W
R/W
R/W
-
R/W
R/W
R/W
-
R/W