LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 146

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 107. Pin description
<Document ID>
User manual
Symbol
P3_3
P3_4
P3_5
B14
A15
C12
x
x
x
…continued
x
x
x
x
x
x
118
119
121
All information provided in this document is subject to legal disclaimers.
[5]
[3]
[3]
Rev. 00.13 — 20 July 2011
Reset
state
[2]
I; PU
I; PU
I; PU
Type Description
-
-
I/O
O
O
-
O
I/O
I/O
-
-
I/O
O
I/O
I/O
O
I/O
-
-
I/O
I
I/O
I/O
O
R — Function reserved.
R — Function reserved.
SSP0_SCK — Serial clock for SSP0.
SPIFI_SCK — Serial clock for SPIFI.
CGU_OUT1 — CGU spare clock output 1.
R — Function reserved.
I2S0_TX_MCLK — I2S transmit master clock.
I2S1_TX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I
GPIO1[14] — General purpose digital input/output pin.
R — Function reserved.
R — Function reserved.
SPIFI_SIO3 — I/O lane 3 for SPIFI.
U1_TXD — Transmitter output for UART 1.
I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the
signal WS in the I
I2S1_RX_SDA — I2S1 Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I
LCD_VD13 — LCD data.
GPIO1[15] — General purpose digital input/output pin.
R — Function reserved.
R — Function reserved.
SPIFI_SIO2 — I/O lane 2 for SPIFI.
U1_RXD — Receiver input for UART 1.
I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I
I2S1_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the
signal WS in the I
LCD_VD12 — LCD data.
Chapter 12: LPC18xx Pin configuration
2
2
2
2
S-bus specification.
S-bus specification.
S-bus specification.
S-bus specification.
2
S-bus specification.
UM10430
© NXP B.V. 2011. All rights reserved.
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