LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 212

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
13.4.10 EMC chip select delay register
Table 122. EMC control delay register (EMCCTRLDELAY, address 0x4008 6D04) bit
This register provides a programmable delay for the EMC chip select outputs. The delay
for each control output is approximately 0.5 ns  XXX_DELAY. (XXX_DELAY = 0x0: delay
 0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.)
Table 123. EMC chip select delay register (EMCCSDELAY, address 0x4008 6D08) bit
Bit
2:0
3
6:4
7
10:8
11
14:12
15
18:16
19
22:20
23
26:24
27
30:28
31
Bit
2:0
3
6:4
7
10:8
11
14:12
15
18:16
19
22:20
23
26:24
Symbol
RAS_DELAY
-
CAS_DELAY
-
OE_DELAY
-
WE_DELAY
-
BLS0_DELAY Delay of the EMC_BLS0 output.
-
BLS1_DELAY Delay of the EMC_BLS1 output.
-
BLS2_DELAY Delay of the EMC_BLS2 clock enable output.
-
BLS3_DELAY Delay of the EMC_BLS3 clock enable output.
-
Symbol
DYCS0_DELAY
-
DYCS1_DELAY
-
DYCS2_DELAY
-
DYCS3_DELAY
-
CS0_DELAY
-
CS1_DELAY
-
CS2_DELAY
description
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Delay of the EMC_RAS output.
Reserved.
Delay of the EMC_CAS output.
Reserved.
Delay of the EMC_OE output.
Reserved.
Delay of the EMC_WE output.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Description
Delay of the EMC_DYCS0 output.
Reserved.
Delay of the EMC_DYCS1 output.
Reserved.
Delay of the EMC_DYCS2 output.
Reserved.
Delay of the EMC_DYCS3 output.
Reserved.
Delay of the EMC_CS0 output.
Reserved.
Delay of the EMC_CS1 output.
Reserved.
Delay of the EMC_CS2 clock enable output.
Chapter 13: LPC18xx System Control Unit (SCU)
UM10430
© NXP B.V. 2011. All rights reserved.
0
Reset
value
0
-
0
-
0
-
0
-
0
-
0
-
Reset
value
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
212 of 1164
Access
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
Access
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-