LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 402

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.8.1.5.1 Micro-frame pipeline
20.8.1.5 Operational model
20.8.1.6 Split state machines
The operational models are well defined for the behavior of the Transaction Translator
(see USB 2.0 specification) and for the EHCI controller moving packets between system
memory and a USB-HS hub. Since the embedded Transaction Translator exists within the
host controller there is no physical bus between EHCI host controller driver and the USB
FS/LS bus. These sections will briefly discuss the operational model for how the EHCI and
Transaction Translator operational models are combined without the physical bus
between. The following sections assume the reader is familiar with both the EHCI and
USB 2.0 Transaction Translator operational models.
The EHCI operational model uses the concept of H-frames and B-frames to describe the
pipeline between the Host (H) and the Bus (B). The embedded Transaction Translator
shall use the same pipeline algorithms specified in the USB 2.0 specification for a
Hub-based Transaction Translator.
It is important to note that when programming the S-mask and C-masks in the EHCI data
structures to schedule periodic transfers for the embedded Transaction Translator, the
EHCI host controller driver must follow the same rules specified in EHCI for programming
the S-mask and C-mask for downstream Hub-based Transaction Translators. Once
periodic transfers are exhausted, any stored asynchronous transfer will be moved.
Asynchronous transfers are opportunistic in that they shall execute whenever possible
and their operation is not tied to H-frame and B-frame boundaries with the exception that
an asynchronous transfer can not babble through the SOF (start of B-frame 0.)
The start and complete split operational model differs from EHCI slightly because there is
no bus medium between the EHCI controller and the embedded Transaction Translator.
Where a start or complete-split operation would occur by requesting the split to the HS
hub, the start/complete split operation is simple an internal operation to the embedded
Transaction Translator. The following table summarizes the conditions where handshakes
are emulated from internal state instead of actual handshakes to HS split bus traffic.
2. siTD (for direct attach FS) – Periodic (ISO Endpoint)
all FS ISO transactions:
Hub Address = (default TTHA = 0)
siTD.EPS = 00 (full speed)
Maximum Packet Size must less than or equal to 1023 or undefined behavior may
result.
Remark: When QH.EPS = 01 (LS) and PORTSCx.PSPD = 00 (FS), a LS-pre-pid
will be sent before the transmitting LS traffic.
Maximum Packet Size must be less than or equal 64 or undefined behavior may
result.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
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