LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 282

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
16.7 Functional description
<Document ID>
User manual
Fig 26. DMA controller block diagram
16.7.1.1 AHB slave interface
16.7.1.2 Control logic and register bank
16.7.1.3 DMA request and response interface
16.7.1.4 Channel logic and channel register bank
16.7.1.5 Interrupt request
16.7.1 DMA controller functional description
responses
AHB Matrix
requests
Interrupt
DMA
DMA
DMA
The DMA Controller enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master.
Controller.
The functions of the DMA Controller are described in the following sections.
All transactions to DMA Controller registers on the AHB slave interface are 32 bits wide.
Eight bit and 16-bit accesses are not supported and will result in an exception.
The register block stores data written or to be read across the AHB interface.
See DMA Interface description for information on the DMA request and response
interface.
The channel logic and channel register bank contains registers and logic required for each
DMA channel.
The interrupt request generates the interrupt to the ARM processor.
AHB Slave
response
Interface
interface
Interrupt
request
request
DMA
and
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
Logic and
Registers
logic and
registers
Channel
Control
Figure 26
Interface
Interface
Master
Master
AHB
AHB
M0
M1
shows a block diagram of the DMA
AHB Matrix
AHB Matrix
UM10430
© NXP B.V. 2011. All rights reserved.
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