LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1066

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 993. Register overview: I2S (base address 0x400A 2000)
<Document ID>
User manual
Name
DAO
DAI
TXFIFO
RXFIFO
STATE
DMA1
DMA2
IRQ
TXRATE
RXRATE
TXBITRATE
RXBITRATE
TXMODE
RXMODE
42.9.6.1 I2S Digital Audio Output register
42.9.6 Register description
Access Address
R/W
R/W
WO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 993
functions. Following the table are details for each register.
Reset value reflects the data stored in used bits only. It does not include reserved bits
content.
The DAO register controls the operation of the I2S transmit channel. The function of bits in
DAO are shown in
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
shows the registers associated with the I2S interface and a summary of their
All information provided in this document is subject to legal disclaimers.
Description
I2S Digital Audio Output Register. Contains control bits for the I2S
transmit channel.
I2S Digital Audio Input Register. Contains control bits for the I2S
receive channel.
I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO.
I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO.
I2S Status Feedback Register. Contains status information about the
I2S interface.
I2S DMA Configuration Register 1. Contains control information for
DMA request 1.
I2S DMA Configuration Register 2. Contains control information for
DMA request 2.
I2S Interrupt Request Control Register. Contains bits that control how
the I2S interrupt request is generated.
I2S Transmit MCLK divider. This register determines the I2S TX MCLK
rate by specifying the value to divide PCLK by in order to produce
MCLK.
I2S Receive MCLK divider. This register determines the I2S RX MCLK
rate by specifying the value to divide PCLK by in order to produce
MCLK.
I2S Transmit bit rate divider. This register determines the I2S transmit
bit rate by specifying the value to divide TX_MCLK by in order to
produce the transmit bit clock.
I2S Receive bit rate divider. This register determines the I2S receive bit
rate by specifying the value to divide RX_MCLK by in order to produce
the receive bit clock.
I2S Transmit mode control.
I2S Receive mode control.
Table
Rev. 00.13 — 20 July 2011
994.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
1066 of 1164
Reset
value
0x87E1
0x07E1
0
0
0x7
0
0
0
0
0
0
0
0
0