LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 382

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 327. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description
<Document ID>
User manual
Bit
0
1
2
Symbol
CCS
CSC
PE
20.6.15.2 Host mode
Value Description
0
1
0
1
0
1
The host controller uses one port. The register is only reset when power is initially applied
or in response to a controller reset. The initial conditions of the port are:
If the port has power control, this state remains until software applies power to the port by
setting port power to one in the PORTSC register.
•
•
Connect status change
Current connect status
This value reflects the current state of the port and may not correspond
directly to the event that caused the CSC bit to be set.
This bit is 0 if PP (Port Power bit) is 0.
Software clears this bit by writing a 1 to it.
No device is present.
Device is present on the port.
Indicates a change has occurred in the port’s Current Connect Status. The
host/device controller sets this bit for all changes to the port device connect
status, even if system software has not cleared an existing connect status
change. For example, the insertion status changes twice before system
software has cleared the changed condition, hub hardware will be setting
an already-set bit (i.e., the bit will remain set). Software clears this bit by
writing a one to it.
This bit is 0 if PP (Port Power bit) is 0
No change in current status.
Change in current status.
Port enable.
Ports can only be enabled by the host controller as a part of the reset and
enable. Software cannot enable a port by writing a one to this field. Ports
can be disabled by either a fault condition (disconnect event or other fault
condition) or by the host software. Note that the bit status does not change
until the port state actually changes. There may be a delay in disabling or
enabling a port due to other host controller and bus events.
When the port is disabled. downstream propagation of data is blocked
except for reset.
This bit is 0 if PP (Port Power bit) is 0.
Port disabled.
Port enabled.
No device connected
Port disabled
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
Reset
value
0
0
0
© NXP B.V. 2011. All rights reserved.
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Access
R/WC
R/WC
R/W