LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1058

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.8.4.3 GPIO port pin value register (PIN)
Table 984. GPIO port mask byte and half-word accessible register description
Writing to the PIN register stores the value in the port output register, bypassing the need
to use both the SET and CLR registers to obtain the entire written value. This feature
should be used carefully in an application since it affects the entire port.
This register provides the value of port pins that are configured to perform digital
functions. A read of this register yields the logic value of the pin regardless of whether the
pin is configured for input or output, as GPIO, or as an alternate digital function. For
example, a particular port pin may have GPIO input, GPIO output, UART receive, and
PWM output as selectable functions. Any configuration of that pin will allow its current
logic state to be read from the corresponding PIN register.
Access to a port pin via the PIN register is masked by the corresponding bit of the MASK
register (see
Only pins masked with zeros in the Mask register (see
to the current content of the GPIO port pin value register.
Remark: If the PINn register is read, its bit(s) masked with 1 in the MASK register will be
set to 0 regardless of the physical pin state.
Generic
register
name
MASKn_0
MASKn_1
MASKn_L
Section
Description
GPIO port x (x = 0 to 4)
mask register 0. Bit 0 in
corresponds to pin
GPIOx_0... bit 7 to pin
GPIOx_7.
GPIO port x mask register
1. Bit 0 corresponds to pin
GPIOx_8... bit 7 to pin
GPIOx_15.
GPIO port x mask Lower
half-word register. Bit 0
corresponds to pin
GPIOx_0... bit 15 to pin
GPIOx_15.
All information provided in this document is subject to legal disclaimers.
42.8.4.2).
Rev. 00.13 — 20 July 2011
Register
length in
bits
/access
8 (byte)/
R/W
8 (byte)/
R/W
16
(half-word)/
R/W
Reset
value
0x0
0x0
0x0
Section
Port x register name -
address
MASK0_0 - 0x400F 0010
MASK1_0 - 0x400F 0030
MASK2_0 - 0x400F 0050
MASK3_0 - 0x400F 0070
MASK4_0 - 0x400F 0090
MASK0_1 - 0x400F 0011
MASK1_1 - 0x400F 0031
MASK2_1 - 0x400F 0051
MASK3_1 - 0400F 0071
MASK4_1 - 0x400F 0091
MASK0_L - 0x400F 0010
MASK1_L - 0x400F 0030
MASK2_L - 0x400F 0050
MASK3_L - 0x400F 0070
MASK4_L - 0x400F 0090
42.8.4.2) will be correlated
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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