LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1136

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 712. SSP0/1 clocking and power control . . . . . . . .770
Table 713. SSP pin description . . . . . . . . . . . . . . . . . . . .771
Table 714. Register overview: SSP0 (base address 0x4008
Table 715. Register overview: SSP1 (base address 0x400C
Table 716: SSP Control Register 0 (CR0 - address
Table 717: SSP Control Register 1 (CR1 - address
Table 718: SSP Data Register (DR - address 0x4008 3008
Table 719: SSP Status Register (SR - address 0x4008 300C
Table 720: SSP Clock Prescale Register (CPSR - address
Table 721: SSP Interrupt Mask Set/Clear register (IMSC -
Table 722: SSP Raw Interrupt Status register (RIS - address
Table 723: SSP Masked Interrupt Status register (MIS
Table 724: SSP interrupt Clear Register (ICR - address
Table 725: SSP DMA Control Register (DMACR - address
Table 726. I2S clocking and power control . . . . . . . . . . .785
Table 727. Pin description . . . . . . . . . . . . . . . . . . . . . . . .788
Table 728. Register overview: I2S0 (base address 0x400A
Table 729. Register overview: I2S1 (base address 0x400A
Table 730. I2S Digital Audio Output register (DAO - address
Table 731. I2S Digital Audio Input register (DAI - address
Table 732. Transmit FIFO register (TXFIFO - address
Table 733. I2S Receive FIFO register (RXFIFO - address
Table 734. I2S Status Feedback register (STATE - address
Table 735. I2S DMA Configuration register 1 (DMA1 -
<Document ID>
User manual
3000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .771
5000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .772
0x4008 3000 (SSP0), 0x400C 5000 (SSP1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .773
0x4008 3004 (SSP0), 0x400C 5004 (SSP1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .774
(SSP0), 0x400C 5008 (SSP1)) bit description 774
(SSP0), 0x400C 500C (SSP1)) bit description775
0x4008 3010 (SSP0), 0x400C 5010 (SSP1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .775
address 0x4008 3014 (SSP0), 0x400C 5014
(SSP1)) bit description . . . . . . . . . . . . . . . . . .776
0x4008 3018 (SSP0), RIS - 0x400C 5018 (SSP1))
bit description . . . . . . . . . . . . . . . . . . . . . . . . .776
-address 0x4008 301C (SSP0), 0x400C 501C
(SSP1)) bit description . . . . . . . . . . . . . . . . . .777
0x4008 3020 (SSP0), ICR - 0x400C 5020
(SSP1)) bit description . . . . . . . . . . . . . . . . . .777
0x4008 3024 (SSP0), 0x400C 5024 (SSP1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .778
2000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .790
3000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .790
0x400A 2000 (I2S0) and 0x400A 3000 (I2S1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .791
0x400A 2004 (I2S0) and 0x400A 3004 (I2S1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .792
0x400A 2008 (I2S0) and 0x400A 3008 (I2S1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .792
0x400A 200C (I2S0) and 0x400A 300C (I2S1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .792
0x400A 2010 (I2S0) and 0x400A 3010 (I2S1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .793
address 0x400A 2014 (I2S0) and 0x400A 3014
(I2S1)) bit description . . . . . . . . . . . . . . . . . . .793
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 736. I2S DMA Configuration register 2 (DMA2 -
Table 737. I2S Interrupt Request Control register (IRQ -
Table 738. I2S Transmit Clock Rate register (TXRATE -
Table 739. I2S Receive Clock Rate register (RXRATE -
Table 740. I2S Transmit Clock Rate register (TXBITRATE -
Table 741. I2S Receive Clock Rate register (RXBITRATE -
Table 742. I2S Transmit Mode Control register (TXMODE -
Table 743. I2S Receive Mode Control register (RXMODE -
Table 744. I2S transmit modes . . . . . . . . . . . . . . . . . . . . 799
Table 745. I2S receive modes . . . . . . . . . . . . . . . . . . . . 802
Table 746. Conditions for FIFO level comparison . . . . . . 804
Table 747. DMA and interrupt request generation . . . . . 804
Table 748. Status feedback in the STATE register . . . . . 804
Table 749. C_CAN clocking and power control . . . . . . . 806
Table 750. C_CAN pin description . . . . . . . . . . . . . . . . . 808
Table 751. Register overview: C_CAN0 (base address
Table 752. Register overview: C_CAN1 (base address
Table 753. CAN control registers (CNTL, address
Table 754. CAN status register (STAT, address 0x400E 2004
Table 755. CAN error counter (EC, address 0x400E 2008
Table 756. CAN bit timing register (BT, address
Table 757. CAN interrupt register (INT, address
Table 758. CAN test register (TEST, address 0x400E 2014
Table 759. CAN baud rate prescaler extension register
address 0x400A 2018 (I2S0) and 0x400A 3018
(I2S1)) bit description. . . . . . . . . . . . . . . . . . . 794
address 0x400A 201C (I2S0) and 0x400A 301C
(I2S1)) bit description. . . . . . . . . . . . . . . . . . . 794
address 0x400A 2020 (I2S0) and 0x400A 3020
(I2S1)) bit description. . . . . . . . . . . . . . . . . . . 795
address 0x400A 2024 (I2S0) and 0x400A 3024
(I2S1)) bit description. . . . . . . . . . . . . . . . . . . 796
address 0x400A 2028 (I2S0) and 0x400A 3028
(I2S1)) bit description. . . . . . . . . . . . . . . . . . . 796
address 0x400A 202C (I2S0) and 0x400A 302C
(I2S1)) bit description. . . . . . . . . . . . . . . . . . . 797
address 0x400A 2030 (I2S0) and 0x400A 3030
(I2S1)) bit description. . . . . . . . . . . . . . . . . . . 797
address 0x400A 2034 (I2S0) and 0x400A 3034
(I2S1)) bit description. . . . . . . . . . . . . . . . . . . 797
0x400E 2000). . . . . . . . . . . . . . . . . . . . . . . . . 809
0x400A 4000). . . . . . . . . . . . . . . . . . . . . . . . . 810
0x400E 2000 (C_CAN0) and 0x400A 4000
(C_CAN1)) bit description
(C_CAN0) and 0x400A 4004 (C_CAN1)) bit
description
(C_CAN0) and 0x400A 4008 (C_CAN1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 815
0x400E 200C (C_CAN0) and 0x400A 400C
(C_CAN1)) bit description . . . . . . . . . . . . . . . 816
0x400E 2010 (C_CAN0) and 0x400A 4010
(C_CAN1)) bit description . . . . . . . . . . . . . . . 816
(C_CAN0) and 0x400A 4014 (C_CAN1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
(BRPE, address 0x400E 2018 (C_CAN0) and
0x400A 4018 (C_CAN1)) bit description . . . . 817
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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