LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 578

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
23.7.11.2.1 Next base address update interrupt
23.7.11.2.2 FIFO underflow interrupt
23.7.11.1 Master bus error interrupt
23.7.11.2 Vertical compare interrupt
23.7.12 LCD power-up and power-down sequence
Each of the four individual maskable interrupts is enabled or disabled by changing the
mask bits in the INT_MSK register. These interrupts are also combined into a single
overall interrupt, which is asserted if any of the individual interrupts are both asserted and
unmasked. Provision of individual outputs in addition to a combined interrupt output
enables use of either a global interrupt service routine, or modular device drivers to
handle interrupts.
The status of the individual interrupt sources can be read from the INTRAW register.
The master bus error interrupt is asserted when an ERROR response is received by the
master interface during a transaction with a slave. When such an error is encountered, the
master interface enters an error state and remains in this state until clearance of the error
has been signaled to it. When the respective interrupt service routine is complete, the
master bus error interrupt may be cleared by writing a 1 to the BERIC bit in the INTCLR
register. This action releases the master interface from its ERROR state to the start of
FRAME state, and enables fresh frame of data display to be initiated.
The vertical compare interrupt asserts when one of four vertical display regions, selected
using the CTRL register, is reached. The interrupt can be made to occur at the start of:
The interrupt may be cleared by writing a 1 to the VcompIC bit in the INTCLR register.
The LCD next base address update interrupt asserts when either the LCDUPBASE or
LCDLPBASE values have been transferred to the LCDUPCURR or LCDLPCURR
incrementers respectively. This signals to the system that it is safe to update the
LCDUPBASE or the LCDLPBASE registers with new frame base addresses if required.
The interrupt can be cleared by writing a 1 to the LNBUIC bit in the INTCLR register
The FIFO underflow interrupt asserts when internal data is requested from an empty DMA
FIFO. Internally, upper and lower panel DMA FIFO underflow interrupt signals are
generated.
The interrupt can be cleared by writing a 1 to the FUFIC bit in the INTCLR register.
The LCD controller requires the following power-up sequence to be performed:
•
•
•
•
•
•
Next base address update interrupt.
FIFO underflow interrupt.
Vertical synchronization.
Back porch.
Active video.
Front porch.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
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