LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 962

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 907. Edge configuration register (EDGE - address 0x4004 4004) bit description
Bit
1
2
3
4
5
6
7
Symbol
WAKEUP1_E
WAKEUP2_E
WAKEUP3_E
ATIMER_E
RTC_E
BOD_E
WWDT_E
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Edge/level detect mode for WAKEUP1 event. The
corresponding bit in the EDGE register must be 0.
Level detect.
Edge detect. Detect falling edge if bit 1 in the HILO
register is 0. Detect rising edge if bit 1 in the HILO
register is 1.
Edge/level detect mode for WAKEUP2 event. The
corresponding bit in the EDGE register must be 0.
Level detect.
Edge detect. Detect falling edge if bit 2 in the HILO
register is 0. Detect rising edge if bit 2 in the HILO
register is 1.
Edge/level detect mode for WAKEUP3 event. The
corresponding bit in the EDGE register must be 0.
Level detect.
Edge detect. Detect falling edge if bit 30 in the HILO
register is 0. Detect rising edge if bit 3 in the HILO
register is 1.
Edge/level detect mode for alarm timer event. The
corresponding bit in the EDGE register must be 0.
Level detect.
Edge detect. Detect falling edge if bit 4 in the HILO
register is 0. Detect rising edge if bit 4 in the HILO
register is 1.
Edge/level detect mode for RTC event. The
corresponding bit in the EDGE register must be 0.
Level detect.
Edge detect. Detect falling edge if bit 5 in the HILO
register is 0. Detect rising edge if bit 5 in the HILO
register is 1.
Edge/level detect mode for BOD event. The
corresponding bit in the EDGE register must be 0.
Level detect.
Edge detect. Detect falling edge if bit 6 in the HILO
register is 0. Detect rising edge if bit 6 in the HILO
register is 1.
Edge/level detect mode for WWDTD event. The
corresponding bit in the EDGE register must be 0.
Level detect.
Edge detect. Detect falling edge if bit 7 in the HILO
register is 0. Detect rising edge if bit 7 in the HILO
register is 1.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0
0