LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 997

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.4.7.4.1 Features
42.4.7.4.2 PLL0 description
42.4.7.4 PLL0 (for USB0)
Table 947. Recommended values for C
The block diagram of the PLL is shown in
clkin. Pin clkout is the PLL clock output. The analog part of the PLL consists of a Phase
Frequency Detector (PFD), filter and a Current Controlled Oscillator (CCO). The PFD has
two inputs, a reference input from the (divided) external clock and one input from the
divided CCO output clock. The PFD compares the phase/frequency of these input signals
and generates a control signal if they don’t match. This control signal is fed to a filter
which drives the CCO.
Fundamental oscillation
frequency F
15 MHz
20 MHz
•
•
•
•
•
•
•
•
•
•
•
Input frequency: 14 kHz to 150 MHz. The input from an external crystal is limited to
25 MHz.
CCO frequency: 275 MHz to 550 MHz.
Output clock range: 4.3 MHz to 550 MHz.
Programmable dividers:
– Pre-divider N (N, 1 to 2
– Feedback-divider 2 x M (M, 1 to 2
– Post-divider P x 2 (P, 1 to 2
Programmable bandwidth (integrating action, proportional action, high frequency
pole).
On-the-fly adjustment of the clock possible (dividers with handshake control).
Positive edge clocking.
Frequency limiter to avoid hang-up of the PLL.
Lock detector.
Power-down mode.
Free running mode
components parameters) high frequency mode
OSC
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Maximum crystal series
resistance R
< 80 
< 80 
< 100 
8
)
5
).
X1/X2
S
15
Figure
in oscillation mode (crystal and external
)
154. The clock input has to be fed to pin
External load capacitors C
C
18 pF, 18 pF
39 pF, 39 pF
47 pF, 47 pF
x2
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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