LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 465

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 389. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description
<Document ID>
User manual
Bit
3
4
5
6
Symbol
PEC
OCA
OCC
FPR
…continued
Value Description
0
0
1
0
1
0
1
Force port resume
Port disable/enable change
For the root hub, this bit gets set to a one only when a port is disabled due
to disconnect on the port or due to the appropriate conditions existing at
the EOF2 point (See Chapter 11 of the USB Specification ). Software clears
this by writing a one to it.
This bit is 0 if PP (Port Power bit) is 0,
No change.
Port enabled/disabled status has changed.
Over-current active
This bit will automatically transition from 1 to 0 when the over-current
condition is removed.
The port does not have an over-current condition.
The port has currently an over-current condition.
Over-current change
This bit gets set to one when there is a change to Over-current Active.
Software clears this bit by writing a one to this bit position.
Software sets this bit to one to drive resume signaling. The Host Controller
sets this bit to one if a J-to-K transition is detected while the port is in the
Suspend state. When this bit transitions to a one because a J-to-K
transition is detected, the Port Change Detect bit in the USBSTS register is
also set to one. This bit will automatically change to zero after the resume
sequence is complete. This behavior is different from EHCI where the host
controller driver is required to set this bit to a zero after the resume duration
is timed in the driver.
Note that when the Host controller owns the port, the resume sequence
follows the defined sequence documented in the USB Specification
Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on the port as
long as this bit remains a one. This bit will remain a one until the port has
switched to the high-speed idle. Writing a zero has no affect because the
port controller will time the resume operation clear the bit the port control
state switches to HS or FS idle.
This bit is 0 if PP (Port Power bit) is 0.
No resume (K-state) detected/driven on port.
Resume detected/driven on port.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
UM10430
Reset
value
0
0
0
0
© NXP B.V. 2011. All rights reserved.
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Access
R/WC
RO
R/WC
R/W