LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 530

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 437. Transmit descriptor word 0 (TDES0)
Bit
6:3
7
8
9
10
11
12
13
14
Symbol
CC/
SLOTNU
M
VF
EC
LC
NC
LC
IPE
FF
JT
All information provided in this document is subject to legal disclaimers.
Description
CC: Collision Count (Status field)
These status bits indicate the number of collisions that occurred before the
frame was transmitted. This count is not valid when the Excessive Collisions
bit (TDES0[8]) is set. The core updates this status field only in the
half-duplex mode.
SLOTNUM: Slot Number Control Bits in AV Mode
These bits indicate the slot interval in which the data should be fetched from
the corresponding buffers addressed by TDES2 or TDES3. When the
transmit descriptor is fetched, the DMA compares the slot number value in
this field with the slot interval maintained in the core (Register 11xx). It
fetches the data from the buffers only if there is a match in values. These bits
are valid only for the AV channels (not channel 0).
VLAN Frame
When set, this bit indicates that the transmitted frame was a VLAN-type
frame.
Excessive Collision
When set, this bit indicates that the transmission was aborted after 16
successive collisions while attempting to transmit the current frame. If the
DR (Disable Retry) bit in the MAC Configuration register is set, this bit is set
after the first collision, and the transmission of the frame is aborted.
Late Collision
When set, this bit indicates that frame transmission was aborted due to a
collision occurring after the collision window (64 byte-times, including
preamble, in MII mode and 512 byte-times, including preamble and carrier
extension, in MII mode). This bit is not valid if the Underflow Error bit is set.
No Carrier
When set, this bit indicates that the Carrier Sense signal form the PHY was
not asserted during transmission.
Loss of Carrier
When set, this bit indicates that a loss of carrier occurred during frame
transmission (that is, the gmii_crs_i signal was inactive for one or more
transmit clock periods during frame transmission). This is valid only for the
frames transmitted without collision when the MAC operates in Half-Duplex
mode.
IP Payload Error
When set, this bit indicates that MAC transmitter detected an error in the
TCP, UDP, or ICMP IP datagram payload.
The transmitter checks the payload length received in the IPv4 or IPv6
header against the actual number of TCP, UDP, or ICMP packet bytes
received from the application and issues an error status in case of a
mismatch.
Frame Flushed
When set, this bit indicates that the DMA/MTL flushed the frame due to a
software Flush command given by the CPU.
Jabber Timeout
When set, this bit indicates the MAC transmitter has experienced a jabber
time-out. This bit is only set when the MAC configuration register’s JD bit is
not set.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
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