LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 299

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 225. Control Register (CTRL, address 0x4000 4000) bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
Symbol
CONTROLLER_RESET
FIFO_RESET
DMA_RESET
-
INT_ENABLE
DMA_ENABLE
18.6.1 Control Register (CTRL)
Table 224. Register overview: SDMMC (base address: 0x4000 4000)
Name
IDINTEN
DSCADDR
BUFADDR
Value
0
1
0
1
0
1
0
1
0
1
Access
R/W
R
R
All information provided in this document is subject to legal disclaimers.
Description
Controller reset. To reset controller, firmware should set bit to 1. This
bit is auto-cleared after two AHB and two cclk_in clock cycles. This
resets:
- BIU/CIU interface
- CIU and state machines
- abort_read_data, send_irq_response, and read_wait bits of Control
register
- start_cmd bit of Command register Does not affect any registers or
DMA interface, or FIFO or host interrupts
No change
Reset DWC_mobile_storage controller
Fifo reset. To reset FIFO, firmware should set bit to 1. This bit is
auto-cleared after completion of reset operation. auto-cleared after
two AHB clocks.
No change
Reset to data FIFO To reset FIFO pointers
dma_reset. To reset DMA interface, firmware should set bit to 1. This
bit is auto-cleared after two AHB clocks.
No change
Reset internal DMA interface control logic
Reserved
Global interrupt enable/disable bit. The int port is 1 only when this bit
is 1 and one or more unmasked interrupts are set.
Disable interrupts
Enable interrupts
DMA enable. Valid only if DWC_mobile_storage configured for
External DMA interface. Even when DMA mode is enabled, host can
still push/pop data into or from FIFO; this should not happen during
the normal operation. If there is simultaneous FIFO access from
host/DMA, the data coherency is lost. Also, there is no arbitration
inside DWC_mobile_storage to prioritize simultaneous host/DMA
access.
Disable DMA transfer mode
Enable DMA transfer mode
Rev. 00.13 — 20 July 2011
Address
offset
0x090
0x094
0x098
Description
Internal DMAC Interrupt Enable
Register
Current Host Descriptor Address
Register
Current Buffer Descriptor Address
Register
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x00000000
0x00000000
0x00000000
299 of 1164
Reset
value
0
0
0
-
0
0