LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 254

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
15.5.1.6 Pin interrupt active level (falling edge interrupt) set register
15.5.1.7 Pin interrupt active level (falling edge interrupt) clear register
Table 175. Pin interrupt active level (falling edge interrupt enable) register (IENF, address
For each of the 8 pin interrupts selected in the PINTSEL registers (see
Table
depending on the pin interrupt mode configured in the ISEL register:
Table 176. Pin interrupt active level (falling edge interrupt) set register (SIENF, address
For each of the 8 pin interrupts selected in the PINTSEL registers (see
Table
depending on the pin interrupt mode configured in the ISEL register:
Bit
7:0
31:8 -
Bit
7:0
31:8
•
•
•
•
If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is
set.
If the pin interrupt mode is level sensitive (PMODE = 1), the HIGH-active interrupt is
selected.
If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is
cleared.
If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is
selected.
Symbol Description
ENAF
131), one bit in the SIENF register sets the corresponding bit in the IENF register
131), one bit in the CIENF register sets the corresponding bit in the IENF register
Symbol
SETENAF Ones written to this address set bits in the IENF, thus
-
0x4008 7010) bit description
0x4008 7014) bit description
Enables the falling edge or configures the active level interrupt
for each pin interrupt. Bit n configures the pin interrupt selected
in PINTSELn.
0 = Disable falling edge interrupt or set active interrupt level
LOW.
1 = Enable falling edge interrupt enabled or set active interrupt
level HIGH.
Reserved.
All information provided in this document is subject to legal disclaimers.
Description
enabling interrupts. Bit n sets bit n in the IENF register.
0 = No operation.
1 = Select HIGH-active interrupt or enable falling edge
interrupt.
Reserved.
Rev. 00.13 — 20 July 2011
Chapter 15: LPC18xx GPIO
UM10430
© NXP B.V. 2011. All rights reserved.
Table 130
Table 130
Reset
value
NA
-
Reset
value
0
-
254 of 1164
Access
WO
-
Access
R/W
-
and
and