LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 989

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.4.6.5 Integer divider register A
Table 938. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0030) bit description
Table 939. IDIVA control register (IDIVA_CTRL, address 0x4005 0034) bit description
Bit
13:12
15:14
23:16
27:24
31:28
Bit
0
1
Symbol
NSEL[1:0]
-
MSEL[7:0]
CLK_SEL
-
Symbol
PD
-
…continued
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value Description
0x0
0x1
0x2
0x3
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Value Description
0
1
Pre-divider division ratio
1
2
3 (default)
4
Reserved
Feedback-divider division ratio (M)
Clock-source selection.
32 kHz oscillator
ENET_RX_CLK
ENET_TX_CLK
GP_CLKIN
Reserved
Crystal oscillator
PLL0
Reserved
Reserved
Reserved
IDIVA
IDIVB
IDIVC
IDIVD
IDIVE
Reserved
IRC (default)
Integer divider A power down
IDIVA enabled (default)
power-down
Reserved
00000000 = 1
00000001 = 2
...
11111111 = 256
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
Reset
value
10
-
11000 R/W
0x01
-
989 of 1164
Access
R/W
-
Access
R/W
-
R/W
-