LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 280

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 215. DMA Channel Configuration registers (CCONFIG, 0x4000 2110 (C0CONFIG) to 0x4000 21F0 (C7CONFIG))
<Document ID>
User manual
Bit
10:6
13:11 FLOWCNTRL
14
15
16
Symbol
DESTPERIPHERAL
IE
ITC
L
bit description
…continued
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Description
Destination peripheral. This value selects the DMA destination
request peripheral. This field is ignored if the destination of the
transfer is to memory. See
Destination = SPIFI
Destination = Timer 0 match 0/UART0 transmit
Destination = Timer 0 match 1/UART0 receive
Destination = Timer 1 match 0/UART1 transmit
Destination = Timer 1 match 1/UART 1 receive
Destination = Timer 2 match 0/UART 2 transmit
Destination = Timer 2 match 1/UART 2 receive
Destination = Timer 3 match 0/UART3 transmit/SCT DMA
request 0
Destination = Timer 3 match 1/UART3 receive/SCT DMA
request 1
Destination = SSP0 receive/I2S channel 0
Destination = SSP0 transmit/I2S channel 1
Destination = SSP1 receive
Destination = SSP1 transmit
Destination = ADC0
Destination = ADC1
Destination = DAC
Flow control and transfer type. This value indicates the flow
controller and transfer type. The flow controller can be the DMA
Controller, the source peripheral, or the destination peripheral.
The transfer type can be memory-to-memory,
memory-to-peripheral, peripheral-to-memory, or
peripheral-to-peripheral.
Refer to
Memory to memory (DMA control)
Memory to peripheral (DMA control)
Peripheral to memory (DMA control)
Source peripheral to destination peripheral (DMA control)
Source peripheral to destination peripheral (destination control)
Memory to peripheral (peripheral control)
Peripheral to memory (peripheral control)
Source peripheral to destination peripheral (source control)
Interrupt error mask. When cleared, this bit masks out the error
interrupt of the relevant channel.
Terminal count interrupt mask. When cleared, this bit masks out
the terminal count interrupt of the relevant channel.
Lock. When set, this bit enables locked transfers.
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Table 216
Rev. 00.13 — 20 July 2011
for the encoding of this field.
Table 195
for details.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
280 of 1164
Access
R/W
R/W
R/W
R/W
R/W