LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 327

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 265. Register overview: External memory controller (base address 0x4000 5000)
[1]
<Document ID>
User manual
Name
STATICWAITOEN1
STATICWAITRD1
STATICWAITPAGE1
STATICWAITWR1
STATICWAITTURN1
-
STATICCONFIG2
STATICWAITWEN2
STATICWAITOEN2
STATICWAITRD2
STATICWAITPAGE2
STATICWAITWR2
STATICWAITTURN2
-
STATICCONFIG3
STATICWAITWEN3
STATICWAITOEN3
STATICWAITRD3
STATICWAITPAGE3
STATICWAITWR3
STATICWAITTURN3
The reset value after warm reset for the CONTROL register is 0x0000 0001.
19.7.1 EMC Control register
The Control register is a read/write register that controls operation of the memory
controller. The control bits can be altered during normal operation.
Access Address
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
offset
0x228
0x22C
0x230
0x234
0x238
0x23C
0x240
0x244
0x248
0x24C
0x250
0x254
0x258
0x25C
0x260
0x264
0x268
0x26C
0x270
0x274
0x278
All information provided in this document is subject to legal disclaimers.
Description
Selects the delay from chip select 1 or address change,
whichever is later, to output enable.
Selects the delay from chip select 1 to a read access.
Selects the delay for asynchronous page mode sequential
accesses for chip select 1.
Selects the delay from chip select 1 to a write access.
Selects the number of bus turnaround cycles for chip select
1.
Reserved.
Selects the memory configuration for static chip select 2.
Selects the delay from chip select 2 to write enable.
Selects the delay from chip select 2 or address change,
whichever is later, to output enable.
Selects the delay from chip select 2 to a read access.
Selects the delay for asynchronous page mode sequential
accesses for chip select 2.
Selects the delay from chip select 2 to a write access.
Selects the number of bus turnaround cycles for chip select
2.
Reserved.
Selects the memory configuration for static chip select 3.
Selects the delay from chip select 3 to write enable.
Selects the delay from chip select 3 or address change,
whichever is later, to output enable.
Selects the delay from chip select 3 to a read access.
Selects the delay for asynchronous page mode sequential
accesses for chip select 3.
Selects the delay from chip select 3 to a write access.
Selects the number of bus turnaround cycles for chip select
3.
Rev. 00.13 — 20 July 2011
Chapter 19: LPC18xx External Memory Controller (EMC)
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x0
0x0000 001F
0x0000 001F
0x0000 001F
0x0000 000F
-
0x0
0x0
0x0
0x0000 001F
0x0000 001F
0x0000 001F
0x0000 000F
-
0x0
0x0
0x0
0x0000 001F
0x0000 001F
0x0000 001F
0x0000 000F
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