LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1113

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
number will be the first Message Object of the FIFO Buffer. The EOB bit of all Message
Objects of a FIFO Buffer except the last have to be programmed to zero. The EOB bits of
the last Message Object of a FIFO Buffer is set to one, configuring it as the End of the
Block.
Reception of messages with FIFO buffers:
matching to a FIFO Buffer are stored into a Message Object of this FIFO Buffer starting
with the Message Object with the lowest message number.
When a message is stored into a Message Object of a FIFO Buffer the NEWDAT bit of this
Message Object is set. By setting NEWDAT while EOB is zero the Message Object is
locked for further write accesses by the Message Handler until the CPU has written the
NEWDAT bit back to zero.
Messages are stored into a FIFO Buffer until the last Message Object of this FIFO Buffer
is reached. If none of the preceding Message Objects is released by writing NEWDAT to
zero, all further messages for this FIFO Buffer will be written into the last Message Object
of the FIFO Buffer and therefore overwrite previous messages.
Reading from a FIFO buffer:
to the IFx Message Buffer registers by writing its number to the IFx Command Request
Register, bits NEWDAT and INTPND in the corresponding Command Mask Register
should be reset to zero (TXRQST/NEWDAT = ‘1’ and ClrINTPND = ‘1’). The values of
these bits in the Message Control Register always reflect the status before resetting the
bits.
To assure the correct function of a FIFO Buffer, the CPU should read out the Message
Objects starting at the FIFO Object with the lowest message number.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
When the CPU transfers the contents of Message Object
Received messages with identifiers
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
1113 of 1164