LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 694

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 623. Watchdog Mode register (MOD - 0x4008 0000) bit description
Once the WDEN, WDPROTECT, or WDRESET bits are set they can not be cleared by
software. Both flags are cleared by an external reset or a Watchdog timer reset.
WDTOF The Watchdog time-out flag is set when the Watchdog times out, when a feed
error occurs, or when WDPROTECT =1 and an attempt is made to write to the TC
register. This flag is cleared by software writing a 0 to this bit.
WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value
specified by WDWARNINT. This flag is cleared when any reset occurs, and is cleared by
software by writing a 1 to this bit.
Watchdog reset or interrupt will occur any time the watchdog is running and has an
operating clock source. Any clock source works in Sleep mode, and the IRC works in
Deep-sleep mode. If a watchdog interrupt occurs in Sleep or Deep-sleep mode, it will
wake up the device.
Bit
0
1
2
3
4
7:5
Symbol
WDEN
WDRESET
WDTOF
WDINT
WDPROTECT
-
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Chapter 30: LPC18xx Windowed Watchdog timer (WWDT)
Description
Watchdog enable bit. This bit is Set Only.
The watchdog timer is stopped.
The watchdog timer is running.
Watchdog reset enable bit. This bit is Set Only.
A watchdog time-out will not cause a chip reset.
A watchdog time-out will cause a chip reset.
Watchdog time-out flag. Set when the watchdog
timer times out, by a feed error, or by events
associated with WDPROTECT, cleared by
software. Causes a chip reset if WDRESET = 1.
This flag is cleared by software writing a 0 to this
bit.
Watchdog interrupt flag. Set when the timer
reaches the value in the WARNINT register.
Cleared by software by writing a 1 to this bit.
Watchdog update mode. This bit is Set Only.
The watchdog time-out value (WDTC) can be
changed at any time.
The watchdog time-out value (WDTC) can be
changed only after the counter is below the value
of WDWARNINT and WDWINDOW.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0
0
0 (Only after
external reset)
0
0
NA
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