LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 318

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 255. Bus Mode Register (BMOD, address 0x4000 4080) bit description
<Document ID>
User manual
Bit
10:8
31:11
Symbol
PBL
-
18.6.32 Poll Demand Register (PLDMND)
18.6.33 Descriptor List Base Address Register (DBADDR)
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Table 256. Poll Demand Register (PLDMND, address 0x4000 4084) bit description
Table 257. Descriptor List Base Address Register (DBADDR, address 0x4000 4088) bit
Bit
31:0
Bit
31:0
Description
Programmable Burst Length. These bits indicate the maximum number of beats to
be performed in one IDMAC transaction. The IDMAC will always attempt to burst
as specified in PBL each time it starts a Burst transfer on the host bus. The
permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of
MSIZE of FIFOTH register. In order to change this value, write the required value to
FIFOTH register. This is an encode value as follows.Transfer unit is either 16, 32,
or 64 bits, based on HDATA_WIDTH. PBL is a read-only value.
1 transfer
4 transfers
8 transfers
16 transfers
32 transfers
64 transfers
128 transfers
256 transfers
Reserved
Symbol
SDL
Symbol
PD
description
All information provided in this document is subject to legal disclaimers.
Description
Start of Descriptor List. Contains the base address of the First
Descriptor. The LSB bits [0/1/2:0] for 16/32/64-bit bus-width) are
ignored and taken as all-zero by the IDMAC internally. Hence
these LSB bits are read-only.
Description
Poll Demand. If the OWN bit of a descriptor is not set, the FSM
goes to the Suspend state. The host needs to write any value
into this register for the IDMAC FSM to resume normal
descriptor fetch operation. This is a write only register. PD bit is
write-only.
Rev. 00.13 — 20 July 2011
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
Reset
value
318 of 1164
Reset
value
0