LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 497

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 421. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description
<Document ID>
User manual
Bit
13:8
15:14
16
22:17
23
24
Symbol
PBL
PR
FB
RPBL
USP
PBL8X
Description
Programmable burst length
These bits indicate the maximum number of beats to be transferred in one DMA
transaction. This will be the maximum value that is used in a single block Read/Write.
The DMA will always attempt to burst as specified in PBL each time it starts a Burst
transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4,
8, 16, and 32. Any other value will result in undefined behavior. When USP is set
high, this PBL value is applicable for TxDMA transactions only.
The PBL values have the following limitations.
The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO
and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a
constraint that the maximum beat supported is half the depth of the FIFO, except
when specified (as given below). For different data bus widths and FIFO sizes, the
valid PBL range (including x8 mode) is provided in the following table. If the PBL is
common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO
depths must be considered. Do not program out-of-range PBL values, because the
system may not behave properly.
Rx-to-Tx priority ratio
RxDMA requests given priority over TxDMA requests in the following ratio. This is
valid only when the DA bit is reset.
00 = 1-to-1
01 = 2-to-1
10 = 3-to-1
11 = 4-to-1
Fixed burst
This bit controls whether the AHB Master interface performs fixed burst transfers or
not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start
of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst
transfer operations.
RxDMA PBL
These bits indicate the maximum number of beats to be transferred in one RxDMA
transaction. This will be the maximum value that is used in a single block Read/Write.
The RxDMA will always attempt to burst as specified in RPBL each time it starts a
Burst transfer on the host bus. RPBL can be programmed with permissible values of
1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are
valid and applicable only when USP is set high.
Use separate PBL
When set high, it configures the RxDMA to use the value configured in bits [22:17] as
PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When
reset to low, the PBL value in bits [13:8] is applicable for both DMA engines.
8 x PBL mode
When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits
[13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64,
128, and 256 beats depending on the PBL value.
Remark: This bit function is not backward compatible. Before version 3.50a, this bit
was 4xPBL.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
1
00
0
1
0
0
497 of 1164
Access
R/W
R/W
R/W
R/W
R/W
R/W