LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 665

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
26.8.8 Interrupts
The MCPWM includes 10 possible interrupt sources:
Section 26.7.9 “MCPWM Interrupt registers”
Section 26.7.2 “PWM Capture Control register”
MCI0-2 inputs to “capture events” on the three channels.
Fig 79. Three-phase AC mode sample waveforms, edge aligned PWM mode
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•
•
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When any channel’s TC matches its Match register.
When any channel’s TC matches its Limit register.
When any channel captures the value of its TC into its Capture register, because a
selected edge occurs on any of MCI0-2.
When all three channels’ outputs are forced to “A passive” state because the
MCABORT pin goes low.
MCOB2
MCOA2
MCOB1
MCOA1
MCOB0
MCOA0
All information provided in this document is subject to legal disclaimers.
0
MAT1
Rev. 00.13 — 20 July 2011
MAT0
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
MAT2
timer reset
LIM0
MAT1
explains how to enable these interrupts, and
describes how to map edges on the
MAT2
timer reset
LIM0
UM10430
© NXP B.V. 2011. All rights reserved.
POLA2 = 0
POLA1 = 0
POLA0 = 0
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