LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1138

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 794. CAN clock divider register (CLKDIV, address
Table 795. Initialization of a transmit object. . . . . . . . . . .846
Table 796. Initialization of a receive object . . . . . . . . . . .847
Table 797. Parameters of the C_CAN bit time. . . . . . . . .851
Table 798. I2C0/1 clocking and power control. . . . . . . . .853
Table 799. I
Table 800. Register overview: I
Table 801. Register overview: I
Table 802. I
Table 803. I
Table 804. I
Table 805. I
Table 806. I
Table 807. I
Table 808. SCLL + SCLH values for selected I
Table 809. I
Table 810. I
Table 811. I
Table 812. I
Table 813. I
Table 814. CONSET used to configure Master mode . . .865
Table 815. CONSET used to configure Slave mode . . . .867
Table 816. Abbreviations used to describe an I
Table 817. CONSET used to initialize Master Transmitter
Table 818. Master Transmitter mode. . . . . . . . . . . . . . . .875
Table 819. Master Receiver mode. . . . . . . . . . . . . . . . . .878
Table 820. ADR usage in Slave Receiver mode . . . . . . .880
Table 821. CONSET used to initialize Slave Receiver mode
<Document ID>
User manual
0x400E 2180 (C_CAN0) and 0x400A 4180
(C_CAN1)) bit description. . . . . . . . . . . . . . . .837
1000)
0000)
0x400A 1000 (I2C0) and 0x400E 0000 (I2C1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .858
(I2C0) and 0x400E 0004 (I2C1)) bit description . .
859
0x400E 0008 (I2C1)) bit description . . . . . . . .860
0x400A 100C (I2C0) and 0x400E 000C (I2C1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .860
address 0x400A 1010 (I2C0) and 0x400E 0010
(I2C1)) bit description . . . . . . . . . . . . . . . . . . .860
0x400A 1014 (I2C0) and 0x400E 0014 (I2C1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .860
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .861
0x400A 1018 and 0x400E 0018 (I2C1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .861
address 0x400A 101C (I2C0) and 0x400E 001C
(I2C1)) bit description . . . . . . . . . . . . . . . . . . .862
0x400A 1020 (ADR1) to 0x400A 1028 (ADR3)
(I2C0) and 0x400E 0020 (ADR1) to 0x400E 0028
(ADR3) (I2C1)) bit description . . . . . . . . . . . .863
address 0x400A 102C (I2C0) and 0x400E 002C
(I2C1)) bit description . . . . . . . . . . . . . . . . . . .864
0x400A 1030 (MASK0) to 0x400A 103C (MASK3)
(I2C0) and 0x400E 0030 (MASK0) to 0x400E
003C (MASK3) (I2C1)) bit description . . . . . .865
873
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .873
2
2
2
2
2
2
2
2
2
2
2
2
C Slave Address registers (ADR - address
C-bus pin description. . . . . . . . . . . . . . . . . .855
C Control Set register (CONSET - address
C Status register (STAT - address 0x400A 1004
C Data register (DAT - 0x400A 1008 (I2C0) and
C Slave Address register 0 (ADR0 - address
C SCL HIGH Duty Cycle register (SCLH -
C SCL Low duty cycle register (SCLL - address
C Control Clear register (CONCLR - address
C Monitor mode control register (MMCTRL -
C Data buffer register (DATA_BUFFER -
C Mask registers (MASK - address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .855
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .856
2
2
C0 (base address 0x400A
C1 (base address 0x400E
All information provided in this document is subject to legal disclaimers.
2
2
C clock
C operation.
Rev. 00.13 — 20 July 2011
Table 822. Slave Receiver mode . . . . . . . . . . . . . . . . . 881
Table 823. Slave Transmitter mode . . . . . . . . . . . . . . . . 885
Table 824. Miscellaneous States . . . . . . . . . . . . . . . . . . 887
Table 825. ADC0/1 clocking and power control . . . . . . . 898
Table 826. ADC pin description . . . . . . . . . . . . . . . . . . . 899
Table 827. Register overview: ADC0 (base address 0x400E
Table 828. Register overview: ADC1 (base address 0x400E
Table 829. A/D Control register (CR - address 0x400E 3000
Table 830. A/D Global Data register (GDR - address
Table 831. A/D Interrupt Enable register (INTEN - address
Table 832. A/D Data registers (DR - addresses 0x400E 3010
Table 833. A/D Status register (STAT - address 0x400E 3030
Table 834. DAC clocking and power control . . . . . . . . . . 906
Table 835. DAC pin description . . . . . . . . . . . . . . . . . . . 906
Table 836. Register overview: DAC (base address 0x400E
Table 837: D/A Converter register (CR - address 0x400E
Table 838. D/A Control register (CTRL - address
Table 839: D/A Converter counter value register (CNTVAL -
Table 840. Flash configuration . . . . . . . . . . . . . . . . . . . . 914
Table 841. Code Read Protection options . . . . . . . . . . . 915
Table 842. Code Read Protection hardware/software
Table 843. ISP command summary . . . . . . . . . . . . . . . . 917
Table 844. ISP Unlock command . . . . . . . . . . . . . . . . . . 917
Table 845. ISP Set Baud Rate command . . . . . . . . . . . . 918
Table 846. Correlation between possible ISP baudrates and
Table 847. ISP Echo command . . . . . . . . . . . . . . . . . . . 918
Table 848. ISP Write to RAM command . . . . . . . . . . . . . 919
Table 849. ISP Read Memory command . . . . . . . . . . . . 919
Table 850. ISP Prepare sector(s) for write operation
Table 851. ISP Copy command . . . . . . . . . . . . . . . . . . . 920
Table 852. ISP Go command . . . . . . . . . . . . . . . . . . . . . 921
Table 853. ISP Erase sector command . . . . . . . . . . . . . 921
Table 854. ISP Blank check sector command . . . . . . . . 922
Table 855. ISP Read Part Identification command . . . . . 922
Table 856. LPC18xx part identification numbers. . . . . . . 922
Table 857. ISP Read Boot Code version number command
880
3000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
(ADC0) and 0x400E 4000 (ADC1)) bit description
901
0x400E 3004 (ADC0) and 0x400E 4004 (ADC1))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 903
0x400E 300C (ADC0) and 0x400E 400C (ADC1))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 904
(DR0) to 0x400E 302C (DR7) (ADC0);
0x400E 4010 (DR0) to 0x400E 402C (DR7)
(ADC1)) bit description. . . . . . . . . . . . . . . . . . 904
(ADC0) and 0x400E 4030 (ADC1)) bit description
905
1000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
1000) bit description. . . . . . . . . . . . . . . . . . . . 907
0x400E 1004) bit description . . . . . . . . . . . . . 907
address 0x400E 1008) bit description . . . . . . 908
interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
CCLK frequency (in MHz) . . . . . . . . . . . . . . . 918
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
922
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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