LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 695

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
30.7.2 Watchdog timer constant register
30.7.3 Watchdog feed register
Table 624. Watchdog operating modes selection
The TC register determines the time-out value. Every time a feed sequence occurs, the
TC register content is reloaded into the Watchdog timer. This is pre-loaded with the value
0x00 00FF upon reset. Writing values below 0xFF will cause 0x00 00FF to be loaded into
the TC register. Thus the minimum time-out interval is T
If the WDPROTECT bit in MOD register is set to one, an attempt to change the value of
TC before the watchdog counter is below the values of WDWARNINT and WDWINDOW
will cause a watchdog reset and set the WDTOF flag.
Table 625. Watchdog Timer Constant register (TC - 0x4008 0004) bit description
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
time-out value in the TC register. This operation will also start the Watchdog if it is enabled
via the MOD register. Setting the WDEN bit in the WDMOD register is not sufficient to
enable the Watchdog. A valid feed sequence must be completed after setting WDEN
before the Watchdog is capable of generating a reset. Until then, the Watchdog will ignore
feed errors. After writing 0xAA to FEED register, access to any Watchdog register other
than writing 0x55 to FEED register causes an immediate reset/interrupt when the
Watchdog is enabled, and sets the WDTOF flag. The reset will be generated during the
second PCLK following an incorrect access to a Watchdog register during a feed
sequence.
Interrupts should be disabled during the feed sequence. An abort condition will occur if an
interrupt happens during the feed sequence.
WDEN
0
1
1
Bit
23:0
31:24
Symbol
WDTC
-
WDRESET
X (0 or 1)
0
1
All information provided in this document is subject to legal disclaimers.
Description
Watchdog time-out value.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Mode of Operation
Debug/Operate without the Watchdog running.
Watchdog interrupt mode: the watchdog warning interrupt will be
generated but watchdog reset will not.
When this mode is selected, the watchdog counter reaching the value
specified by WDWARNINT will set the WDINT flag and the Watchdog
interrupt request will be generated.
Watchdog reset mode: Both the watchdog interrupt and watchdog reset
are enabled.
When this mode is selected, the watchdog counter reaching the value
specified by WDWARNINT will set the WDINT flag and the Watchdog
interrupt request will be generated. The watchdog counter reaching zero
will reset the microcontroller.
Remark: Other causes for a watchdog reset are: A watchdog feed or
changing the WDTC value (if the WDPROTECT bit is set in the MOD
register) before reaching the value of WDWINDOW.
Chapter 30: LPC18xx Windowed Watchdog timer (WWDT)
WDCLK
 256  4.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x00 00FF
NA
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