LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1108

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Fig 175. Block diagram of a message object transfer
APB
bus
42.10.7.3.1 Management of message objects
IF1 COMMAND REQUEST
IF2 COMMAND REQUEST
COMMAND REGISTERS
IF1 COMMAND MASK
IF2 COMMAND MASK
IF1 ARBITRATION 1/2
MESSAGE BUFFER
IF2 ARBITRATION 1/2
IF1 MESSAGE CTRL
IF2 MESSAGE CTRL
IF1 DATA A1/2
IF1 DATA B1/2
IF2 DATA A1/2
IF2 DATA B1/2
REGISTERS
IF1 MASK1, 2
IF2 MASK1, 2
INTERFACE
The configuration of the Message Objects in the Message RAM will (with the exception of
the bits MSGVAL, NEWDAT, INTPND, and TXRQST) is not be affected by resetting the
chip. All the Message Objects must be initialized by the CPU or they must be set to not
valid (MSGVAL = ‘0’).The bit timing must be configured before the CPU clears the INIT bit
in the CAN Control Register.
The configuration of a Message Object is done by programming Mask, Arbitration, Control
and Data field of one of the two interface register sets to the desired values. By writing to
the corresponding IFx Command Request Register, the IFx Message Buffer Registers are
loaded into the addressed Message Object in the Message RAM.
When the INIT bit in the CAN Control Register is cleared, the CAN Protocol Controller
state machine of the CAN core and the Message Handler State Machine control the CAN
controller’s internal data flow. Received messages that pass the acceptance filtering are
stored into the Message RAM, and messages with pending transmission request are
loaded into the CAN core’s shift register and are transmitted via the CAN bus.
The CPU reads received messages and updates messages to be transmitted via the IFx
Interface Registers. Depending on the configuration, the CPU is interrupted on certain
CAN message and CAN error events.
message object
All information provided in this document is subject to legal disclaimers.
read transfer
transfer a
write transfer
Rev. 00.13 — 20 July 2011
TRANSMISSION REQUEST 1/2
INTERRUPT PENDING1/2
MESSAGE OBJECT 32
MESSAGE OBJECT 1
MESSAGE OBJECT 2
MESSAGE HANDLER
MESSAGE VALID1/2
MESSAGE RAM
NEW DATA 1/2
.
.
.
SHIFT REGISTERS
CAN CORE/
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
CAN frame
transfer a
receive
transmit
1108 of 1164
CAN
bus