LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 816

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
36.6.1.4 CAN bit timing register
36.6.1.5 CAN interrupt register
Table 756. CAN bit timing register (BT, address 0x400E 200C (C_CAN0) and 0x400A 400C
[1]
Remark: With a module clock CAN_CLK of 8 MHz, the reset value of 0x2301 configures
the C_CAN for a bit rate of 500 kBit/s. The registers are only writable if a configuration
change is enabled in CANCTRL and the controller is initialized by software (bits CCE and
INIT in the CAN Control Register are set).
Table 757. CAN interrupt register (INT, address 0x400E 2010 (C_CAN0) and 0x400A 4010
If several interrupts are pending, the CAN Interrupt Register will point to the pending
interrupt with the highest priority, disregarding their chronological order. An interrupt
remains pending until the CPU has cleared it. If INTID is different from 0x0000 and IE is
set, the interrupt line to the CPU is active. The interrupt line remains active until INTID is
back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
The Status Interrupt has the highest priority. Among the message interrupts, the Message
Object’ s interrupt priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object’s INTPND bit. The
StatusInterrupt is cleared by reading the Status Register.
Bit
5:0
7:6
11:8
14:12
31:15
Bit
15:0
31:16
Hardware interprets the value programmed into these bits as the bit value  1.
Symbol
BRP
SJW
TSEG1
TSEG2
-
Symbol
INTID15_0 0x0000 = No interrupt is pending
-
(C_CAN1)) bit description
(C_CAN1)) bit description
All information provided in this document is subject to legal disclaimers.
Description
Baud rate prescaler
The value by which the oscillator frequency is divided
for generating the bit time quanta. The bit time is built up
from a multiple of this quanta. Valid values for the Baud
Rate Prescaler are 0 to 63
Valid programmed values are 0x01 - 0x3F
(Re)synchronization jump width
Valid programmed values are 0 to 3
Time segment after the sample point
Valid values are 0 to 7
Time segment before the sample point
Valid values are 1 to 15
Reserved
Description
0x0001 to 0x0020 = Number of message object which
caused the interrupt.
0x0021 to 0x7FFF = Unused
0x8000 = Status interrupt
0x8001 to 0xFFFF = Unused
Reserved
Rev. 00.13 — 20 July 2011
[1]
[1]
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Chapter 36: LPC18xx C_CAN
Reset
value
0
-
UM10430
Reset
value
1
0
0011
010
-
© NXP B.V. 2011. All rights reserved.
Access
R
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Access
R/W
R/w
R/W
R/W
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