LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1116

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.10.7.5.1 Bit time and bit rate
CAN supports bit rates in the range of lower than 1 kBit/s up to 1000 kBit/s. Each member
of the CAN network has its own clock generator, usually a quartz oscillator. The timing
parameter of the bit time (i.e. the reciprocal of the bit rate) can be configured individually
for each CAN node, creating a common bit rate even though the CAN nodes’ oscillator
periods (f
The frequencies of these oscillators are not absolutely stable, as small variations are
caused by changes in temperature or voltage and by deteriorating components. As long
as the variations remain inside a specific oscillator tolerance range (df), the CAN nodes
are able to compensate for the different bit rates by re-synchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments
The Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific,
programmable number of time quanta (see
(t
clock f and the Baud Rate Prescaler (BRP): t
is the frequency C_CAN peripheral clock.
The Synchronization Segment Sync_Seg is the part of the bit time where edges of the
CAN bus level are expected to occur; the distance between an edge that occurs outside of
Sync_Seg and the Sync_Seg is called the phase error of that edge. The Propagation
Time Segment Prop_Seg is intended to compensate for the physical delay times within
the CAN network. The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 surround
the Sample Point. The (Re-)Synchronization Jump Width (SJW) defines how far a
re-synchronization may move the Sample Point inside the limits defined by the Phase
Buffer Segments to compensate for edge phase errors.
Table 1048
Bit time parameters are programmed through the BT register,
bit timing and examples, see the C_CAN user’s manual, revision 1.2 .
Table 1048.Parameters of the C_CAN bit time
Parameter
BRP
SYNC_SEG
PROP_SEG
TSEG1
TSEG2
SJW
q
), which is the basic time unit of the bit time, is defined by the CAN controller’s system
osc
describes the minimum programmable ranges required by the CAN protocol.
) may be different.
All information provided in this document is subject to legal disclaimers.
Range
(1...32)
1t
(1...8)  t
(1...8)  t
(1...8)  t
(1...4)  t
q
Rev. 00.13 — 20 July 2011
q
q
q
q
Function
Defines the length of the time quantum t
Synchronization segment. Fixed length. Synchronization
of bus input to system clock.
Propagation time segment. Compensates for physical
delay times. This parameter is determined by the system
delay times in the C_CAN network.
Phase buffer segment 1. May be lengthened temporarily
by synchronization.
Phase buffer segment 2. May be shortened temporarily by
synchronization.
(Re-) synchronization jump width. May not be longer than
either phase buffer segment.
Table
q
= BRP / f
1048). The length of the time quantum
sys
. The C_CAN’s system clock f
Table
Chapter 42: Appendix
1019. For details on
UM10430
© NXP B.V. 2011. All rights reserved.
q
.
(Figure
1116 of 1164
177).
sys