LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 834

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
36.6.3.1 CAN transmission request 1 register
36.6.3.2 CAN transmission request 2 register
36.6.3 Message handler registers
Table 785. CAN message interface data B2 registers (IF2_DB2, address 0x400E 20A8
All Message Handler registers are read-only. Their contents (TXRQST, NEWDAT,
INTPND, and MSGVAL bits of each Message Object and the Interrupt Identifier) is status
information provided by the Message Handler FSM.
This register contains the TXRQST bits of message objects 1 to 16. By reading out the
TXRQST bits, the CPU can check for which Message Object a Transmission Request is
pending. The TXRQST bit of a specific Message Object can be set/reset by the CPU via
the IFx Message Interface Registers or by the Message Handler after reception of a
Remote Frame or after a successful transmission.
Table 786. CAN transmission request 1 register (TXREQ1, address 0x400E 2100 (C_CAN0)
This register contains the TXRQST bits of message objects 32 to 17. By reading out the
TXRQST bits, the CPU can check for which Message Object a Transmission Request is
pending. The TXRQST bit of a specific Message Object can be set/reset by the CPU via
the IFx Message Interface Registers or by the Message Handler after reception of a
Remote Frame or after a successful transmission.
Table 787. CAN transmission request 2 register (TXREQ2, address 0x400E 2104 (C_CAN0)
Bit
7:0
15:8
31:16
Bit
15:0
31:16 -
Bit
15:0
31:16 -
Symbol
TXRQST16_1 Transmission request bit of message objects 16 to 1.
Symbol
TXRQST32_17
Symbol Description
DATA6
DATA7
-
(C_CAN0) and 0x400A 40A8 (C_CAN1)) bit description
and 0x400A 4100 (C_CAN1)) bit description
and 0x400A 4104 (C_CAN1)) bit description
All information provided in this document is subject to legal disclaimers.
Data byte 6
Data byte 7
Reserved
Description
0 = This message object is not waiting for
transmission.
1 = The transmission of this message object is
requested and not yet done.
Reserved
Rev. 00.13 — 20 July 2011
Description
Transmission request bit of message objects 32 to 17.
0 = This message object is not waiting for
transmission.
1 = The transmission of this message object is
requested and not yet done.
Reserved
Chapter 36: LPC18xx C_CAN
Reset value Access
0x00
0x00
-
UM10430
-
© NXP B.V. 2011. All rights reserved.
Reset
value
0x00
Reset
value
0x00
-
R/W
R/W
-
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Access
R
-
Access
R
-