LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 752

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 697: UART1 FIFO Control Register (FCR - address 0x4008 2008) bit description
<Document ID>
User manual
Bit
1
2
3
5:4
7:6
31:8
Symbol
RXFIFORES
TXFIFORES
DMAMODE
-
RXTRIGLVL
-
33.5.6.1 DMA Operation
33.5.7 UART1 Line Control Register
Value Description
0
1
0
1
0x0
0x1
0x2
0x3
The user can optionally operate the UART transmit and/or receive using DMA. The DMA
mode is determined by the DMA Mode Select bit in the FCR register. Note that for DMA
operation as for any operation of the UART, the FIFOs must be enabled via the FIFO
Enable bit in the FCR register.
UART receiver DMA
In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO
level becoming equal to or greater than trigger level, or if a character time-out occurs. See
the description of the RX Trigger Level above. The receiver DMA request is cleared by the
DMA controller.
UART transmitter DMA
In DMA mode, the transmitter DMA request is asserted on the event of the transmitter
FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA
controller.
The U1LCR determines the format of the data character that is to be transmitted or
received.
RX FIFO Reset.
No impact on either of UART1 FIFOs.
Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx FIFO, reset the
pointer logic. This bit is self-clearing.
TX FIFO Reset.
No impact on either of UART1 FIFOs.
Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX FIFO, reset the
pointer logic. This bit is self-clearing.
DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this
bit selects the DMA mode. See
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
RX Trigger Level. These two bits determine how many receiver UART1 FIFO
characters must be written before an interrupt is activated.
Trigger level 0 (1 character or 0x01).
Trigger level 1 (4 characters or 0x04).
Trigger level 2 (8 characters or 0x08).
Trigger level 3 (14 characters or 0x0E).
Reserved, user software should not write ones to reserved bits.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Section
33.5.6.1.
Chapter 33: LPC18xx UART1
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0
0
0
NA
0
NA
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