LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 951

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 890. Interrupt Clear-Pending Register 0 register (ICPR0 - address 0xE000 E280) bit description
Table 891. Interrupt Active Bit Register 0 (IABR0 - address 0xE000 E300) bit description
<Document ID>
User manual
Bit
24
25
26
27
28
29
30
31:
30
Bit
0
1
2
4:3
5
6
Symbol
ICP_USART0
ICP_UART1
ICP_USART2
ICP_USART3
ICP_I2S
ICP_AES
ICP_SPIFI
-
Symbol
IAB_DAC
IAB_ER
IAB_DMA
-
IAB_ETHERNE
T
IAB_SDIO
42.1.8.5 Interrupt Active Bit Register 0
Description
DAC interrupt active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
Event router interrupt active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
DMA interrupt active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
Ethernet interrupt active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
SDIO interrupt active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
The IABR0 register is a read-only register that allows reading the active state of the first
32 peripheral interrupts. This allows determining which peripherals are asserting an
interrupt to the NVIC. An interrupt may also be pending if enabled.
Description
USART0 interrupt pending clear.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
UART1 interrupt pending clear.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
USART2 interrupt pending clear.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
USART3 interrupt pending clear.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
I2S interrupt pending clear.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
AES interrupt pending clear.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
SPIFI interrupt pending clear.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
Reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0
Reset
value
0
0
0
0
0
0
0
0