LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 381
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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Table 326. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description
<Document ID>
User manual
Bit
19:16 PTC3_0
20
21
22
23
24
25
27:26 PSPD
31:28 -
Symbol
-
-
-
PHCD
PFSC
-
Value Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
-
-
0
1
0
1
-
0x0
0x1
0x2
-
Port test control
J_STATE
K_STATE
PHY low power suspend - clock disable (PLPSCD)
Port force full speed connect
reserved
Port speed
Any value other than 0000 indicates that the port is operating in test mode.
The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the
test mode support specified in the EHCI specification. Writing the PTC field
to any of the FORCE_ENABLE_HS/FS/LS values will force the port into
the connected and enabled state at the selected speed. Writing the PTC
field back to TEST_MODE_DISABLE will allow the port state machines to
progress normally from that point. Values 0111 to 1111 are not valid.
TEST_MODE_DISABLE
SE0 (host)/NAK (device)
Packet
FORCE_ENABLE_HS
FORCE_ENABLE_FS
Not used in device mode. This bit is always 0 in device mode.
Not used in device mode. This bit is always 0 in device mode.
Not used in device mode. This bit is always 0 in device mode.
In device mode, The PHY can be put into Low Power Suspend – Clock
Disable when the device is not running (USBCMD Run/Stop = 0) or the
host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend
will be cleared automatically when the host has signaled resume. Before
forcing a resume from the device, the device controller driver must clear
this bit.
Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the
PHY clock (enabled).
Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the
PHY clock (disabled).
Port connects at any speed.
Writing this bit to a 1 will force the port to only connect at full speed. It
disables the chirp sequence that allows the port to identify itself as
High-speed. This is useful for testing FS configurations with a HS host, hub
or device.
This register field indicates the speed at which the port is operating.
Full-speed
invalid in device mode
High-speed
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
0
0
0
Reset
value
0000
0
0
0
-
© NXP B.V. 2011. All rights reserved.
381 of 1164
-
-
-
R/W
Access
R/W
R/W
RO
-
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