LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 958

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.2.4 Event router inputs
42.2.5 Pin description
42.2.6 Register description
Table 902. Event router inputs
Table 903. Event router pin description
Table 904. Register overview: Event router (base address 0x4004 4000)
Event # Source
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Pin
WAKEUP0/1/2/3
Name
HILO
EDGE
-
WAKEUP0
WAKEUP1
WAKEUP2
WAKEUP3
Alarm timer
RTC
BOD
WWDT
Ethernet
USB0
USB1
-
C_CAN
Combined timer output 2
Combined timer output 6
QEI
Combined timer output 14 Output 14 of the combined timer (ORed output of SCT
-
-
Reset
All information provided in this document is subject to legal disclaimers.
R/W
Access
R/W
-
Rev. 00.13 — 20 July 2011
Direction
I
Address
offset
0x000
0x004
0x008 -
0xFD4
Notes
WAKEUP0 pin
WAKEUP1 pin
WAKEUP2 pin
WAKEUP3 pin
Alarm timer interrupt
RTC interrupt
BOD interrupt
WWDT interrupt
Wake-up packet indicator
Wake-up request
ahb_needclk signal
Reserved
C_CAN interrupt
Output 2 of the combined timer (ORed output of SCT
output 2 and the match channel 2 of timer 0). See
Figure
Output 6 of the combined timer (ORed output of SCT
output 6 and the match channel 2 of timer 1). See
Figure
QEI interrupt
output 14 and the match channel 2 of timer 3). See
Figure
Reserved
Reserved
<tbd>
Description
External wake-up input; can raise an interrupt and can
cause wake-up from any of the low power modes.
178.
178.
178.
Description
Level configuration register
Edge configuration
Reserved
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
Value
0x000
0x000
-
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