LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 132

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
11.4.4.3 Reset external status register 2 for MASTER_RST
11.4.4.4 Reset external status register 4 for WWDT_RST
11.4.4.5 Reset external status register 5 for CREG_RST
Table 101. Reset external status register 1 (RESET_EXT_STAT1, address 0x4005 3404) bit
Table 102. Reset external status register 2 (RESET_EXT_STAT2, address 0x4005 3408) bit
Table 103. Reset external status register 4 (RESET_EXT_STAT4, address 0x4005 3410) bit
Table 104. Reset external status register 5 (RESET_EXT_STAT5, address 0x4005 3414) bit
Bit
0
1
31:2
Bit
1:0
2
31:3
Bit
0
1
31:2
Bit
0
1
31:2
-
Symbol
PERIPHERAL_RESET Reset activated by PERIPHERAL_RST
-
Symbol
-
CORE_RESET
-
Symbol
-
CORE_RESET
-
Symbol
-
CORE_RESET Reset activated by CORE_RST output. Write 0 to
-
description
description
description
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Reserved. Do not modify; read as logic 0.
clear.
0 = Reset not activated
1 = Reset activated
Reserved. Do not modify; read as logic 0.
Description
Reserved. Do not modify; read as logic 0.
output. Write 0 to clear.
0 = Reset not activated
1 = Reset activated
Reserved. Do not modify; read as logic 0.
Description
Reserved. Do not modify; read as logic 0.
Reset activated by CORE_RST output. Write
0 to clear.
0 = Reset not activated
1 = Reset activated
Reserved. Do not modify; read as logic 0.
Description
Reserved. Do not modify; read as logic 0.
Reset activated by CORE_RST output. Write
0 to clear.
0 = Reset not activated
1 = Reset activated
Reserved. Do not modify; read as logic 0.
Chapter 11: LPC18xx Reset Generation Unit (RGU)
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
Reset
value
0
0
0
Reset
value
0
0
0
Reset
value
0
0
0
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Access
-
R/W
-
Access
-
R/W
-
Access
-
R/W
-
Access
-
R/W
-