LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 905

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
38.7 Operation
<Document ID>
User manual
38.7.1 Hardware-triggered conversion
38.7.2 Interrupts
38.7.3 DMA control
Table 833. A/D Status register (STAT - address 0x400E 3030 (ADC0) and 0x400E 4030
If the BURST bit in the ADCR is 0 and the START field contains any value between 0x2
and 0x6, the A/D converter will start a conversion when a transition occurs on a selected
pin or Timer signal. The choices include the two ADCTRIG external input pins, an output
from the motocon PWM, and two combined timer outputs (see
An interrupt is requested to the Vectored Interrupt Controller (VIC) when the ADINT bit in
the ADSTAT register is 1. The ADINT bit is one when any of the DONE bits of A/D
channels that are enabled for interrupts (via the ADINTEN register) are one. Software can
use the Interrupt Enable bit in the VIC that corresponds to the ADC to control whether this
results in an interrupt. The result register for an A/D channel that is generating an interrupt
must be read in order to clear the corresponding DONE flag.
A DMA transfer request is generated from the ADC interrupt request line. To generate a
DMA transfer the same conditions must be met as the conditions for generating an
interrupt. A pending DMA request is cleared after the DMA has read from the requesting
channel’s A/D data register (DR[7:0]). Reading from the global data register (GDR) does
not clear any pending DMA requests.
For DMA transfers, only burst requests are supported. The burst size can be set to one in
the DMA channel control register (see
equal to one of the other DMA-supported burst sizes (applicable DMA burst sizes are 1, 4,
8), set the burst size to one.
The DMA transfer size determines when a DMA interrupt is generated. The transfer size
can be set to the number of ADC channels being converted (see
Non-contiguous channels can be transferred by the DMA using the scatter/gather linked
lists (see
Bit
7:0
15:8
16
31:17 -
Symbol
DONE
OVERUN
ADINT
Section
(ADC1)) bit description
All information provided in this document is subject to legal disclaimers.
16.8.5).
Description
These bits mirror the DONE status flags that appear in the result
register for each A/D channel.
These bits mirror the OVERRRUN status flags that appear in the
result register for each A/D channel. Reading ADSTAT allows
checking the status of all A/D channels simultaneously.
This bit is the A/D interrupt flag. It is one when any of the individual
A/D channel Done flags is asserted and enabled to contribute to the
A/D interrupt via the ADINTEN register.
Reserved. Always 0.
Rev. 00.13 — 20 July 2011
Table
214). If the number of ADC channels is not
Chapter 38: LPC18xx 10-bit ADC0/1
Section
Section
UM10430
38.6.1).
© NXP B.V. 2011. All rights reserved.
16.6.19).
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Reset
value
0
0
0
0