LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1135

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 667. UART Divisor Latch MSB Register when
Table 668. UART Interrupt Enable Register when DLAB = 0
Table 669. UART Interrupt Identification Register, read only
Table 670. UART Interrupt Handling . . . . . . . . . . . . . . . .718
Table 671. UART FIFO Control Register Write Only (FCR -
Table 672. UART Line Control Register (LCR - addresses
Table 673. UART Line Status Register Read Only (LSR -
Table 674. UART Scratch Pad Register (SCR - addresses
Table 675. Autobaud Control Register (ACR - addresses
Table 676. IrDA Control Register (ICR - address
Table 677. IrDA Pulse Width . . . . . . . . . . . . . . . . . . . . . .727
Table 678. UART Fractional Divider Register (FDR -
Table 679. Fractional Divider setting look-up table . . . . .730
Table 680. UART Half duplex enable register (HDEN -
Table 681. UART Smart card interface control register
Table 682. UART RS485 Control register (RS485CTRL -
Table 683. UART RS485 Address Match register
Table 684. UART RS485 Delay value register (RS485DLY -
<Document ID>
User manual
DLAB = 1 (DLM - addresses 0x4008 1004
(UART0), 0x400C 1004 (UART2), 0x400C 2004
(UART3)) bit description . . . . . . . . . . . . . . . . .716
(IER - addresses 0x4008 1004 (UART0), 0x400C
1004 (UART2), 0x400C 2004 (UART3) ) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .716
(IIR - addresses 0x4008 1008 (UART0), 0x400C
1008 (UART2), 0x400C 2008 (UART3)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .717
addresses 0x4008 1008 (UART0), 0x400C 1008
(UART2), 0x400C 2008 (UART3)) bit description.
719
0x4008 100C (UART0), 0x400C 100C (UART2),
0x400C 200C (UART3)) bit description . . . .720
addresses 0x4008 1014 (UART0), 0x400C 1014
(UART2), 0x400C 2014 (UART3) ) bit description
721
0x4008 101C (UART0), 0x400C 101C (UART2),
0x400C 201C (UART3)) bit description . . . . .723
0x4008 1020 (UART0), 0x400C 1020 (UART2),
0x400C 2020 (UART3)) bit description. . . . . .723
0x4000 8024) bit description . . . . . . . . . . . . .726
addresses 0x4008 1028 (UART0), 0x400C 1028
(UART2), 0x400C 2028 (UART3)) bit description.
728
addresses 0x4008 1040 (UART0), 0x400C 1040
(UART2), 0x400C 2040 (UART3)) bit description
731
(SCICTRL - addresses 0x4008 1048 (UART0),
0x400C 1048 (UART2), 0x400C 2048 (UART3))
bit description . . . . . . . . . . . . . . . . . . . . . . . .731
addresses 0x4008 104C (UART0), 0x400C 104C
(UART2), 0x400C 204C (UART3)) bit description
732
(RS485ADRMATCH - addresses 0x4008 1050
(UART0), 0x400C 1050 (UART2), 0x400C 2050
(UART3)) bit description . . . . . . . . . . . . . . . . .733
addresses 0x4008 1054 (UART0), 0x400C 1054
(UART2), 0x400C 2054 (UART3)) bit description.
734
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 685. UART Synchronous mode control registers
Table 686. UART Transmit Enable Register (TER -
Table 687. UART1 clocking and power control . . . . . . . . 743
Table 688: UART1 Pin description . . . . . . . . . . . . . . . . . 744
Table 689: Register overview: UART1 (base address 0x4008
Table 690: UART1 Receiver Buffer Register when DLAB = 0
Table 691: UART1 Transmitter Holding Register when
Table 692: UART1 Divisor Latch LSB Register when
Table 693: UART1 Divisor Latch MSB Register when
Table 694: UART1 Interrupt Enable Register when DLAB = 0
Table 695: UART1 Interrupt Identification Register (IIR -
Table 696: UART1 Interrupt Handling . . . . . . . . . . . . . . . 750
Table 697: UART1 FIFO Control Register (FCR - address
Table 698: UART1 Line Control Register (LCR - address
Table 699: UART1 Modem Control Register (MCR - address
Table 700: Modem status interrupt generation . . . . . . . . 755
Table 701: UART1 Line Status Register (LSR - address
Table 702: UART1 Modem Status Register (MSR - address
Table 703: UART1 Scratch Pad Register (SCR - address
Table 704: Autobaud Control Register (ACR - address
Table 705: UART1 Fractional Divider Register (FDR -
Table 706. Fractional Divider setting look-up table . . . . . 764
Table 707: UART1 Transmit Enable Register (TER - address
Table 708: UART1 RS485 Control register (RS485CTRL -
Table 709. UART1 RS485 Address Match register
Table 710. UART1 RS485 Delay value register (RS485DLY -
Table 711. UART1 FIFO Level register (FIFOLVL - address
(SYNCCTRL - address addresses 0x4008 1058
(UART0), 0x400C 1058 (UART2), 0x400C 2058
(UART3)) bit description. . . . . . . . . . . . . . . . . 734
addresses 0x4008 1030 (UART0), 0x400C 1030
(UART2), 0x400C 205C (UART3)) bit description
736
2000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
(RBR - address 0x4008 2000 ) bit description . .
747
DLAB = 0 (THR - address 0x4008 2000 ) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
DLAB = 1 (DLL - address 0x4008 2000 ) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
DLAB = 1 (DLM - address 0x4008 2004 ) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
(IER - address 0x4008 2004 ) bit description. 748
address 0x4008 2008) bit description . . . . . . 749
0x4008 2008) bit description . . . . . . . . . . . . . 751
0x4008 200C) bit description . . . . . . . . . . . . . 753
0x4008 2010) bit description . . . . . . . . . . . . . 753
0x4008 2014) bit description . . . . . . . . . . . . . 756
0x4008 2018) bit description . . . . . . . . . . . . . 758
0x4008 2014) bit description . . . . . . . . . . . . . 758
0x4008 2020) bit description . . . . . . . . . . . . . 759
address 0x4008 2028) bit description . . . . . . 762
0x4008 2030) bit description . . . . . . . . . . . . . 765
address 0x4008 204C) bit description . . . . . . 765
(RS485ADRMATCH - address 0x4008 2050) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
address 0x4008 2054) bit description . . . . . . 766
0x4008 2058) bit description . . . . . . . . . . . . . 768
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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