LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 653

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
26.7.9.5 MCPWM Interrupt Flags set address
Table 565. MCPWM Interrupt flags read address (INTF - 0x400A 0068) bit description
Writing one(s) to this write-only address sets the corresponding bit(s) in INTF, thus
possibly simulating hardware interrupt(s).
Table 566. MCPWM Interrupt Flags set address (INTF_SET - 0x400A 006C) bit description
Bit
8
9
10
14:11 -
15
31:16 -
Bit
0
1
2
3
4
5
6
7
Symbol
ILIM2_F
IMAT2_F
ICAP2_F
ABORT_F
Symbol
ILIM0_F_SET
IMAT0_F_SET
ICAP0_F_SET
-
ILIM1_F_SET
IMAT1_F_SET
ICAP1_F_SET
-
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Description
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Reserved.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Reserved.
Limit interrupt flag for channel 2.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Match interrupt flag for channel 2.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Capture interrupt flag for channel 2.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Reserved.
Fast abort interrupt flag.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Reserved.
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
UM10430
© NXP B.V. 2011. All rights reserved.
653 of 1164
Reset
value
-
-
-
-
-
-
-
-
Reset
value
0
0
0
-
0
-