LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1132

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 510. SCT output register (OUTPUT - address 0x4000
Table 511. SCT bidirectional output control register
Table 512. SCT conflict resolution register (RES - address
Table 513. SCT DMA 0 request register (DMAREQ0 -
Table 514. SCT DMA 1 request register (DMAREQ1 -
Table 515. SCT flag enable register (EVEN - address 0x4000
Table 516. SCT event flag register (EVFLAG - address
Table 517. SCT conflict enable register (CONEN - address
Table 518. SCT conflict flag register (CONFLAG - address
Table 519. SCT match registers 0 to 15 (MATCH - address
Table 520. SCT capture registers 0 to 15 (CAP - address
Table 521. SCT match reload registers 0 to 15 (MATCHREL-
Table 522. SCT capture control registers 0 to 15 (CAPCTRL-
Table 523. SCT event state mask registers 0 to 15
Table 524. SCT event control register 0 to 15 (EVCTRL -
Table 525. SCT output set register 0 to 15 (OUTPUTSET -
Table 526. SCT output set register 0 to 15 (OUTPUTCL -
Table 527. Event conditions . . . . . . . . . . . . . . . . . . . . . .613
Table 528. Alternate address map for DMA halfword access
Table 529. SCT configuration example . . . . . . . . . . . . . .619
Table 530. Timer0/1/2/3 clocking and power control . . . .621
Table 531. Timer0/1/2/3 pin description . . . . . . . . . . . . .622
Table 532. Timer/Counter function description . . . . . . . .623
Table 533. Register overview: Timer0/1/2/3 (register base
<Document ID>
User manual
description . . . . . . . . . . . . . . . . . . . . . . . . . . .600
0050) bit description . . . . . . . . . . . . . . . . . . . .600
(OUTPUTDIRCTRL - address 0x4000 0054) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .600
0x4000 0058) bit description
address 0x4000 005C) bit description . . . . . .605
address 0x4000 0060) bit description. . . . . . .605
00F0) bit description . . . . . . . . . . . . . . . . . . . .605
0x4000 00F4) bit description . . . . . . . . . . . . .605
0x4000 00F8) bit description . . . . . . . . . . . . .606
0x4000 00FC) bit description . . . . . . . . . . . . .606
0x4000 0100 (MATCH0) to 0x4000 4013C
(MATCH15)) bit description (REGMODEn bit = 0)
607
0x4000 0100 (CAP0) to 0x4000 013C (CAP15))
bit description (REGMODEn bit = 1). . . . . . . .607
address 0x4000 0200 (MATCHRELOAD0) to
0x4000 023C (MATCHRELOAD15) bit description
(REGMODEn bit = 0) . . . . . . . . . . . . . . . . . . .607
address 0x4000 0200 (CAPCTRL0) to 0x4000
023C (CAPCTRL15)) bit description
(REGMODEn bit = 1) . . . . . . . . . . . . . . . . . . .608
(EVSTATEMSK - addresses 0x4000 0300
(EVSTATEMSK0) to 0x4000 0378
(EVSTATEMSK15)) bit description . . . . . . . . .608
address 0x4000 0304 (EVCTRL0) to 0x4000
037C (EVCTRL15)) bit description . . . . . . . . .609
address 0x4000 0500 (OUTPUTSET0) to 0x4000
0578 (OUTPUTSET15)) bit description . . . . .610
address 0x4000 0504 (OUTPUTCL0) to 0x4000
057C (OUTPUTCL15)) bit description . . . . . .610
614
addresses 0x4008 4000 (TIMER0), 0x4008 5000
(TIMER1), 0x400C 3000 (TIMER2), 0x400C 4000
. . . . . . . . . . . .602
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Rev. 00.13 — 20 July 2011
Table 534. Timer interrupt registers IR(IR - addresses
Table 535. Timer control register TCR (TCR - addresses
Table 536. Timer counter registers TC (TC - addresses
Table 537. Timer prescale registers PR (PR - addresses
Table 538. Timer prescale counter registers PC(PC -
Table 539. Timer match control registers MCR (MCR -
Table 540. Timer match registers MR0 to 3 (MR, addresses
Table 541. Timer capture control registers (CCR - addresses
Table 542. Timer capture registers CR0 to 3 (CR, address
Table 543. Timer external match registers (EMR - addresses
Table 544. External Match Control . . . . . . . . . . . . . . . . . 631
Table 545. Timer count control register CTCR(CTCR -
Table 546. PWM clocking and power control . . . . . . . . . 635
Table 547. Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . 638
Table 548. Register overview: Motor Control Pulse Width
Table 549. MCPWM Control read address (CON -
(TIMER3)) . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1),
0x400C 3000 (TIMER3), 0x400C 4000 (TIMER4))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 624
0x4008 4004 (TIMER0), 0x4008 5004 (TIMER1),
0x400C 3003 (TIMER2), 0x400C 4004 (TIMER3))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 625
0x4008 4008 (TIMER0), 0x4008 5008 (TIMER1),
0x400C 3008 (TIMER2), 0x400C 4008 (TIMER3))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 625
0x4008 400C (TIMER0), 0x4008 500C (TIMER1),
0x400C 300C (TIMER2), 0x400C 400C
(TIMER3)) bit description . . . . . . . . . . . . . . . . 625
addresses 0x4008 4010 (TIMER0), 0x4008 5010
(TIMER1), 0x400C 3010 (TIMER2), 0x400C 4010
(TIMER3)) bit description . . . . . . . . . . . . . . . . 626
addresses 0x4008 4014 (TIMER0), 0x4008 5014
(TIMER1), 0x400C 3014 (TIMER2), 0x400C 4014
(TIMER3)) bit description . . . . . . . . . . . . . . . 626
0x4008 4018 (MR0) to 0x4008 4024 (M3)
(TIMER0), 0x4008 5018 (MR0) to 0x4008 5024
(MR3)(TIMER1), 0x400C 3018 (MR0) to 0x400C
8024 (MR3) (TIMER2), 0x400C 4018 (MR0) to
0x400C 4024 (MR3)(TIMER3)) bit description627
0x4008 4028 (TIMER0), 0x4008 5020 (TIMER1),
0x400C 3028 (TIMER2), 0x400C 4028 (TIMER3))
bit description . . . . . . . . . . . . . . . . . . . . . . . . 628
0x4008 402C (CR0) to 0x4008 4038 (CR3)
(TIMER0), 0x4008 502C (CR0) to 0x4008 5038
(CR3) (TIMER1), 0x400C 302C (CR0) to 0x400C
3038 (CR3) (TIMER2), 0x400C 402C (CR0) to
0x400C 4038 (CR3) (TIMER3)) bit description . .
629
0x4008 403C (TIMER0), 0x4008 503C (TIMER1),
0x400C 303C (TIMER2), 0x400C 403C
(TIMER3)) bit description . . . . . . . . . . . . . . . . 630
addresses 0x4008 4070 (TIMER0), 0x4008 5070
(TIMER1), 0x400C 3070 (TIMER2), 0x400C 4070
(TIMER3)) bit description . . . . . . . . . . . . . . . 632
Modulator (MCPWM) (base address 0x400A
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
0x400A 0000) bit description . . . . . . . . . . . . . 639
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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