LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 503

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 428. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description
<Document ID>
User manual
Bit
0
1
2
4:3
5
6
7
12:8
Symbol
-
SR
OSF
RTC
-
FUF
FEF
-
Description
Reserved
Start/stop receive
When this bit is set, the Receive process is placed in the Running state. The DMA
attempts to acquire the descriptor from the Receive list and processes incoming
frames. Descriptor acquisition is attempted from the current position in the list, which
is the address set by the DMA_REC_DES_ADDR register or the position retained
when the Receive process was previously stopped. If no descriptor is owned by the
DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT
register) is set. The Start Receive command is effective only when reception has
stopped. If the command was issued before setting the DMA_REC_DES_ADDR,
DMA behavior is unpredictable.
Operate on second frame
When this bit is set, this bit instructs the DMA to process a second frame of Transmit
data even before status for first frame is obtained.
Receive threshold control
These two bits control the threshold level of the MTL Receive FIFO. Transfer
(request) to DMA starts when the frame size within the MTL Receive FIFO is larger
than the threshold. In addition, full frames with a length less than the threshold are
transferred automatically. Note that value of 11 is not applicable if the configured
Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero,
and are ignored when the RSF bit is set to 1.
00 = 64
01 = 32
10 = 96
11 = 128
Reserved
Forward undersized good frames
When set, the Rx FIFO will forward Undersized frames (frames with no Error and
length less than 64 bytes) including pad-bytes and CRC).
When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already
transferred due to lower value of Receive Threshold (e.g., RTC = 01).
Forward error frames
When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision
error, GMII_ER, giant frame, watchdog timeout, overflow). However, if the frame’s
start byte (write) pointer is already transferred to the read controller side (in Threshold
mode), then the frames are not dropped. . When FEF is set, all frames except runt
error frames are forwarded to the DMA. But when RxFIFO overflows when a partial
frame is written, then such frames are dropped even when FEF is set.
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
0
0
503 of 1164
Access
RO
R/W
R/W
R/W
RO
R/W
R/W
RO