LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1146

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
43.5 Contents
Chapter 1: Introductory information
1.1
1.2
1.3
Chapter 2: LPC18xx Memory mapping
2.1
2.2
2.3
2.3.1
2.3.2
Chapter 3: LPC18xx Boot ROM
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
Chapter 4: LPC18xx Security features
4.1
4.2
4.3
Chapter 5: LPC18xx NVIC
5.1
5.2
5.3
5.4
Chapter 6: LPC18xx Event router
6.1
6.2
6.3
6.4
6.5
6.6
<Document ID>
User manual
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering information (flashless parts
LPC1850/30/20/10) . . . . . . . . . . . . . . . . . . . . . . . 7
How to read this chapter . . . . . . . . . . . . . . . . . 14
Basic configuration . . . . . . . . . . . . . . . . . . . . . 14
Memory configuration . . . . . . . . . . . . . . . . . . . 14
How to read this chapter . . . . . . . . . . . . . . . . . 22
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Functional description . . . . . . . . . . . . . . . . . . 22
How to read this chapter . . . . . . . . . . . . . . . . . 33
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General description . . . . . . . . . . . . . . . . . . . . . 33
How to read this chapter . . . . . . . . . . . . . . . . . 36
Basic configuration . . . . . . . . . . . . . . . . . . . . . 36
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
General description . . . . . . . . . . . . . . . . . . . . . 36
How to read this chapter . . . . . . . . . . . . . . . . . 40
Basic configuration . . . . . . . . . . . . . . . . . . . . . 40
General description . . . . . . . . . . . . . . . . . . . . . 40
Event router inputs . . . . . . . . . . . . . . . . . . . . . 41
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 41
Register description . . . . . . . . . . . . . . . . . . . . 42
On-chip static RAM . . . . . . . . . . . . . . . . . . . . 14
On-chip flash . . . . . . . . . . . . . . . . . . . . . . . . . 15
AES capable devices . . . . . . . . . . . . . . . . . . . 24
Boot process. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Boot image format . . . . . . . . . . . . . . . . . . . . . 26
Boot image creation . . . . . . . . . . . . . . . . . . . . 27
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
1.4
1.5
1.6
2.3.3
2.4
2.5
2.6
3.3.4.1
3.3.4.2
3.3.4.3
3.3.4.4
3.3.4.5
3.3.5
3.3.6
4.4
4.4.1
4.4.2
5.5
5.6
5.7
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
Ordering information (parts with on-chip flash).
8
Block diagram (flashless parts
LPC1850/30/20/10). . . . . . . . . . . . . . . . . . . . . . 10
Block diagram (parts with on-chip flash) . . . 12
General description . . . . . . . . . . . . . . . . . . . . 16
Memory map (flashless parts LPC1850/30/20/10)
17
Memory map (parts with on-chip flash) . . . . 19
AES API calls. . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 37
Register description . . . . . . . . . . . . . . . . . . . . 38
Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
UART boot mode . . . . . . . . . . . . . . . . . . . . . . 28
SPIFI boot mode . . . . . . . . . . . . . . . . . . . . . . 29
EMC boot modes . . . . . . . . . . . . . . . . . . . . . . 30
SPI boot mode . . . . . . . . . . . . . . . . . . . . . . . . 31
Boot process timimg . . . . . . . . . . . . . . . . . . . 31
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Security API . . . . . . . . . . . . . . . . . . . . . . . . . . 34
OTP memory . . . . . . . . . . . . . . . . . . . . . . . . . 35
Level configuration register . . . . . . . . . . . . . . 42
Edge configuration register . . . . . . . . . . . . . . 44
Interrupt clear enable register . . . . . . . . . . . . 47
Event set enable register . . . . . . . . . . . . . . . . 48
Event status register . . . . . . . . . . . . . . . . . . . 49
Event enable register . . . . . . . . . . . . . . . . . . . 50
Clear status register. . . . . . . . . . . . . . . . . . . . 51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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