LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 615

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.7.10.1.1 Configure the counter
24.7.10.1.2 Configure the match and capture registers
24.7.10.1 Configure the SCT
24.7.10 SCT operation
In its simplest, single-state configuration, the SCT operates as an event controlled uni- or
bidirectional counter. Events can be configured to be counter match events, an input or
output level, transitions on an input or output pin, or a combination of match and
input/output behavior. In response to an event, the SCT’s output or outputs can transition
or the SCT can perform other actions such as creating an interrupt or starting, stopping, or
resetting the counter. Multiple simultaneous actions are allowed for each event.
Furthermore, one specific action of the SCT can be triggered by any number of events.
An event is defined uniquely by an action or multiple actions of the SCT. A state is defined
by which events are enabled to trigger an SCT action or actions in any stage of the
counter. Events not selected for this state are ignored.
In a multi-state configuration, states change in response to events. A state change is an
additional action that the SCT can perform when the event occurs. When an event is
configured to change the state, the new state defines a new set of events resulting in
different actions of the SCT. Through multiple cycles of the counter, events can change
the state multiple times and thus create a large variety of event controlled transitions on
the SCT’s outputs and/or interrupts.
Once configured, the SCT can run continuously without software intervention and can
generate multiple output patterns entirely under the control of events.
To set up the SCT for multiple events and states perform the following configuration steps:
1. Configure the L and H counters in the CONFIG register by selecting two independent
2. Select the SCT clock source in the CONFIG register (fields CLKMODE and CLKSEL)
1. Select how many match and capture registers are needed by the application (total of
2. Define match conditions for each match register selected:
•
•
•
To configure the SCT, see
To start, run, and stop the SCT, see
To configure the SCT without in using multiple states as simple event controlled
counter/timer, see
16-bit counters (L counter and H counter) or one combined 32-bit counter in the
UNIFY field.
from any of the inputs or an internal clock.
up to 16):
– In the REGMODE register, select for each of the 16 match/capture register pairs
– Each match register MATCH allows to set one match value if a 32-bit counter is
whether the register is used as a match register or capture register.
used or two match values if the L and H 16-bit counters are used.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Section
Section
24.7.10.3.
Chapter 24: LPC18xx State Configurable Timer (SCT)
24.7.10.1.
Section
24.7.10.2.
UM10430
© NXP B.V. 2011. All rights reserved.
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