LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 727

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.12 UART Fractional Divider Register (U0FDR - 0x4000 8028)
Table 676. IrDA Control Register (ICR - address 0x4000 8024) bit description
The PulseDiv bits in U3ICR are used to select the pulse width when the fixed pulse width
mode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits
should be set so that the resulting pulse width is at least 1.63 µs.
possible pulse widths.
Table 677. IrDA Pulse Width
The UART Fractional Divider Register (FDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at the user’s discretion. This pre-scaler takes
the APB clock and generates an output clock according to the specified fractional
requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 3 or greater.
Bit
1
2
5:3
31:6 -
FixPulseEn
0
1
1
1
1
1
1
1
1
Symbol
IRDAINV
FIXPULSEEN
PULSEDIV
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
NA
Rev. 00.13 — 20 July 2011
PulseDiv
x
0
1
2
3
4
5
6
7
Serial input direction.
The serial input is not inverted.
The serial input is inverted. This has no effect on the
serial output.
IrDA fixed pulse width mode.
IrDA fixed pulse width mode disabled.
IrDA fixed pulse width mode enabled.
Configures the pulse when FixPulseEn = 1. See
Table 677
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
for details.
Chapter 32: LPC18xx USART0_2_3
IrDA Transmitter Pulse width (µs)
3 / (16  baud rate)
2  T
4  T
8  T
16  T
32  T
64  T
128  T
256  T
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
Table 677
UM10430
© NXP B.V. 2011. All rights reserved.
shows the
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Reset
value
0
0
0
0